Alan Zubatch wrote:
Hello,
I am trying to implement the USRP2 FPGA HDL using Xilinx ISE 11.1. I have
set-up the file structure and the project options per the makefile for
U2_rev3. It will synthesize and translate (39 BRAM) but fails map with
44BRAM. The BRAM usage at map failure is:
Alan,
I have never seen that problem before, but I use 10.1.03, not 11.1. Are
you just trying to build the SVN release? Are you able to use 10.l
instead of 11.1?
The problem looks like it's in the Xilinx FIFO core, so maybe if you
rebuild it with coregen from 11.1 it will work better.
Please let me know how it goes, since I have been considering an upgrade
to 11.1 myself.
Thanks,
Matt
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