Ulrika Uppman wrote:
Hi, I'm thinking about how to receive data in a wider frequency range
width the USRP2, and I stumbled over some questions:
Is it possible to set the decimation rate less than 4? All the
documentation I have found is saying that 4 is the least
interpolation/decimation value, but is there any actual constraints
in the hardware that makes it impossible to use a decimation of 2?
With a decimation rate 2 I understand that I will have to send the
data in 8 bit per sample instead of 16 bit per sample over the wire.
Has anyone implemented this functionality for the USRP2, or do the
non-implemented parts have anything to do with the upcoming VRT work?
It should be possible to do what you want with some changes to the FPGA
code. However, we have not put any effort in to doing this because some
of this would have to be redone after the move to VRT.
Matt
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