On Sunday 20 September 2009 22:45:08 Newman, Timothy wrote:
> It totally depends on where you implement the latency sensitive components.
>   I believe the best USB can do is a minimum of 100us, and that probably
>  the theoretical minimum.  If you need 80-120 us latency, you will
>  definitely need to move the latency sensitive components to the FPGA.

The best you can do with USB is 150-200us, if you use really small USB 
transfers (~16bytes), and 250-400  if you use the default block size of 512 
bytes. For small transfers, latency is dominated by IRQ coalescing - there is 
just one interrupt per microframe, resulting in a variable delay of 0-125us 
[1]. For larger transfers, the time needed for filling a USB packet (128 
samples/sample_rate) and transferring it ( (55+512byte) /60MByte/s) 
contributes to latency significantly.

Reducing the packet size to 128 bytes hardly influences the achievable USB 
transfer rate (~40MB/s, [2]), but lowers the theoretical latency signicantly, 
although it will cause higher processing overhead on the host. As far as I 
know, there is no possibility to disable irq coalescing.

Stefan

[1] see Intel EHCI specification
[2] USB 2.0 spec, Table 5-10

-- 
Stefan Brüns  /  Bergstraße 21  /  52062 Aachen
phone: +49 241 53809034     mobile: +49 151 50412019


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