I'm trying to make some modifications to the FPGA of the USRP2 which involves using more multipliers and I came across this error during the Mapping phase of the compile:
ERROR:Place:665 - The design has 31 block-RAM components of which 13 block-RAM components require the adjacent multiplier site to remain empty. This is because certain input pins of adjacent block-RAM and multiplier sites share routing ressources. In addition, the design has 28 multiplier components. Therefore, the design would require a total of 41 multiplier sites on the device. The current device has only 40 multiplier sites. Looking through Xilinx's support and Googling, I've found that the 512x36 BRAM and the multipliers share interconnects, so that you cannot use both, you either need to use less multipliers, less block RAMs, or reduce the input width of the BRAMs to 18 bits. I've tried reducing the number of block RAMs used by changing the RAM_SIZE parameter in u2_core to 16384 instead of 32768. This reduced the number of block RAMs, but this did not change the number of block RAMs that require an empty multiplier. I'd like to know where the 512x36 BRAMs are that cause this problem and if anyone has encountered this problem and found a workaround. I'm currently using rev. 11641 from the 3.2 release branch and building on Xilinx 9.2i Thanks, Kyle _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
