Hello Eric, In USRP1, I don't want AD9862 to use in my application for many reasons.
Am looking for changing four parallel pipes of ADC's into two parallel pipes of ADC's(having interleaved IQ as in the case of DAC's). I need only changes required to be done in FPGA. Although i know that the ADC data bus to FPGA will have to be clocked twice the sampling rate. I believe this may be a minimal change required in the FPGA. Can anyone support me for doing this change. Regards Sanjay
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