On 01/29/2011 01:24 PM, Phil Behnke wrote: > Thanks again, Marcus! Do you suggest breaking the signal up into I > and Q via analog mixing and having two ADCs (one for I and one for Q)? > I was thinking about mixing down to DC and sampling with a single > ADC, and then breaking the signal up into I and Q digitally on the PC > side. I've been looking at the Mercury SDR ( > http://openhpsdr.org/wiki/index.php?title=MERCURY) and that seems like > what they do, only they have a digital down converter in the FPGA > which beaks the signal into I and Q. > > -Phil If you want to convert to I and Q in an FPGA, you need to use a conventional IF architecture that brings it into the range of the ADC sampling rate. If you convert to DC in "real" mode, you lose phase information and have the problem of "folding" about DC.
Use an analog approach to generating I & Q. The simplest is to use a so-called 2XLO approach, in which you generate a 50%-duty-cycle square wave at exactly twice the desired Fc, feed that to a pair of D flip-flops to produce two signals at exactly half the frequency, and exactly 90 degrees out-of-phase with respect to each other. Then use a pair of mixers to produce the converted I & Q signals. Use a dual-channel ADC, like the AD9288 -- only $8.00 apiece for 40Msps, and you can likely find cheaper dual-channel ADCs for only 1 or 2Msps. The FX2 FIFO is 16-bits wide, so if you use a dual-channel 8-bit ADC, you don't have to play any interleaving games into the FX2. Here's an article on a 2XLO approach here, see figure 4: rfdesign.com/mag/606RFDF3.pdf Since your input frequency would be around 40MHz, you could use pretty-ordinary CMOS gates and flip-flops to do this--nothing exotic like ECL logic required. -- Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org
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