Hi all, I compile uhd fpga code meet a lot of errors. I use quartus II 9.1 web edition. I directly open the fpga project file(EttusResearch-UHD-Mirror-81e891f\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf) then choose menu Processing->start compilation then meet a lot of errors. I think the errors major cause by some file can not be found like that: Error (10054): Verilog HDL File I/O error at adc_interface.v(3): can't open Verilog Design File "../../firmware/include/fpga_regs_common.v"
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