the code below is in sdr_lib/rssi.v I don't understand especially this line:
rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
wire [11:0] abs_adc = adc[11] ? ~adc : adc;
reg [25:0] rssi_int;
always @(posedge clock)
if(reset | ~enable)
rssi_int <= #1 26'd0;
else
rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
assign rssi = rssi_int[25:10];
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