You can't reliably get a fixed, known phase-offset because the synthesizers on most cards are fractional-N synthesizers, and they have a random phase offset every time they're retuned or reset.
This is standard behavior for frac-N synthesizers, and not peculiar to USRP hardware. The only exception is the the SBX card, which has experimental code to use a special SYNC feature to allow initial phase offsets to be the same across multiple SBX. This requires both new UHD drivers, and new FPGA code to make it work. On Tue, 17 Apr 2012 05:42:51 -0700 (PDT), RuneS wrote: > Hello on the list, > > Im using Gnuradio 3.3.0, for other reasons, thus is the only option for me > for this project. However Im currently trying to make a 180 phase difference > from Tx_A to Tx_B, of the same signal on a USRP1. > > Hence i make my signal source, like : > > src = gr.sig_source_c(100000, gr.GR_CONST_WAVE, 1, 0) > > my sink: tx = usrp.sink_c(0, nchan=2, fusb_block_size = 1024, > fusb_nblocks=4, fpga_filename=fpga) > > make interleaver: intl = gr.interleave(gr.sizeof_gr_complex) > > make a complex 180' phase turner for my Tx_B branch: multip_B = > gr.multiply_const_cc((-1 - 0j)) > > connect like so: > > self.connect(src, (intl, 0)) > self.connect(src, multip_B, (intl,1)) > self.connect(intl, tx) > > I get signal on both Tx outputs, however i have a 4 db signal level > difference, and every time i run my program i get a different phase > difference, between my two outputs? Im using a network analyser, to check > the difference. It looks pretty random? > > Lastly my daughterboards are from 3-10-2006. From earlier maling list > replies i understand that they are already made to run on FPGA clock, which > fits with a steady phase difference, however is random for everytime i run > my program. I dont see 180' as i expect + the phase keeps changing, for > every run. There is no noticeable driff when the program is running. > > Hope im clear, or else please reply question, and i'll clarify as i can.
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