On Thu, Feb 21, 2013 at 02:10:24PM +0100, Nemanja Savic wrote: > Preamble is indeed long. On the figure I attached in my first post it can be > seen the input and output od > synchronization M&M block. I am expecting this block to do synchronization > based on preamble.
Your packet sync, but not your clock sync (how would the M&M even know about your preamble?). > Not quite sure that I understand, but I am sampling signal with ca. 500k, and > symbol rate is 19.2k, so if you were thinking about oversampling after bit > slicer, yes i have oversampling of ca. 25. Yeah, that's probably over the top. Filter and decimate, that saves clock cycles and possibly improves your SNR. > In my receiver, after a bit filtered demodulated signal from quadrature FM > demodulator, I have a block, designed by myself, that does bit slicing. It is > basically simulation of a circuit that is used in > > some receivers with min and max diode detector circuits. Since I am quite sure > this is not the usual way of doing this, how am I supposed to get digital > pulses from demodulated signal. I recommend parsing gr-digital/python/gmsk.py for an idea how this could be done (though, granted, that doesn't work perfect either, but also doesn't sync via preamble). MB -- Karlsruhe Institute of Technology (KIT) Communications Engineering Lab (CEL) Dipl.-Ing. Martin Braun Research Associate Kaiserstraße 12 Building 05.01 76131 Karlsruhe Phone: +49 721 608-43790 Fax: +49 721 608-46071 www.cel.kit.edu KIT -- University of the State of Baden-Württemberg and National Laboratory of the Helmholtz Association
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