Wolfgang:
You may find the skeleton code (derived from a GRC file) attached here to be useful. Note that for 4 DDCs, you'll need the 4rx FPGA image.
on May 26, 2013, Josh Blum <j...@ettus.com> wrote:
On 05/26/2013 01:10 PM, Wolfgang Buesser wrote:
> Hello
>
> I am using a usrp1 populated with 2 LFRX and 2 LFTX daughter boards.
>
> I want to use the 2 ADC of LFRX-A to sample s different signals.
>
> To do this I use set_subdev_spec("A:A B:A",0).
>
> In order to avoid a segmentation fault I apparently have to create the rx with num_channels=2.
>
> But now I get the error-message:
>
>
> RuntimeError: gr uhd usrp source(4): insufficient connected output ports (2 needed, 1 connected)
>
> My questions:
> 1) Is the num_channels argument to uhd.usrp_source specifying the number of active DDCs?
>
> 2) How do I connect more than 1 port to uhd.usrp_source? In pre-uhd this was achieved using gr.deinterleave - but this does not seem to work anymore.
>
The block has 2 output ports in this case.
-josh
> Here is the code:
>
> #!/usr/bin/python
>
> from gnuradio import gr
> from gnuradio import uhd
> from gnuradio.eng_option import eng_option
>
>
> class build_block(gr.top_block):
> def __init__(self):
> gr.top_block.__init__(self)
>
> self.u_tx = uhd.usrp_sink("serial=47432785",uhd.stream_args('fc32'))
> self.siggen_tx = gr.sig_source_c(self.u_tx.get_samp_rate(),gr.GR_CONST_WAVE,0, 1.0, 0)
> # self.head_tx = gr.head(gr.sizeof_gr_complex, 1000000)
> self.head_tx = gr.head(gr.sizeof_gr_complex, 1000)
> self.u_tx.set_subdev_spec("A:AB",0)
> self.u_tx.set_center_freq(10e6)
> self.u_tx.set_samp_rate(1e6)
> self.u_tx.get_samp_rate()
>
>
> # self.u_rx = uhd.usrp_source("serial=47432785",uhd.stream_args('fc32'),num_channels=1)
> self.u_rx = uhd.usrp_source("serial=47432785",io_type=uhd.io_type.COMPLEX_FLOAT32,num_channels=2)
> # self.u_rx.set_subdev_spec("A:A B:A",0)
> self.u_rx.set_subdev_spec("A:A B:A",0)
> self.u_rx.set_center_freq(10e6+1e3)
> self.u_rx.set_samp_rate(250e3)
> self.head_rx_0 = gr.head(gr.sizeof_gr_complex, 1000)
> self.dst0 = gr.file_sink(gr.sizeof_gr_complex, "r.dat")
>
> # self.di = gr.deinterleave(gr.sizeof_gr_complex)
>
> # self.connect (self.siggen_tx,self.head_tx, self.u_tx)
> self.connect (self.u_rx,self.head_rx_0,self.dst0)
> # self.connect (self.u_rx,self.di)
>
> tb = build_block ()
> tb.run ()
>
> Thanks
>
> Wolfgang
>
>
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usrp1_4chan_rx.py
Description: Binary data
usrp1_4chan_rx.grc
Description: Binary data
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