Hi Weidong, so you can write software for the PS as linux user mode process, I don't know what interface your custom IP exposes so it's hard to give guidance. The Zynq platform relies on AXI interfaces. If your IP uses older busses you might be able to find bridges in Xilinx's coregen. You might want to look into RFNoC if you do any kind of streaming based design. We don't plan to support any kind of XPS workflow at this point.
Cheers, Moritz On Mon, Apr 13, 2015 at 10:02 AM, lassena <[email protected]> wrote: > Hi Moritz, > > Thanks for your reply. > > I need to migrate a project realized on virtix4 to E310. This project has > custom ip code of digital signal process on the both side of PS and PL. And > we use the standalone system in Microblaze. > > If I don't misunderstand you, you mean the fpga project which I downloaded > from git can be modified only in the PL? Is it possible I could get a > version of XPS project I can custom my own design on the both side PS and > PL? > > Thanks again, > > > > <http://twitter.com/lassenaets> <http://twitter.com/lassenaets> > <http://twitter.com/lassenaets>* <http://twitter.com/lassenaets> > <http://www.facebook.com/lassena.etsmtl.ca>* > > > > > > > > > > > > > > *Weidong Wang | Étudiant à la MaîtriseLaboratoire LASSENADépartement du > génie électriqueÉcole de technologie supérieure | 1100, rue Notre-Dame > Ouest | Montréal (Qc) Canada | H3C 1K3Tel.: 514 396-8800, poste 7930 | > Bureau : A-2566 | www.etsmtl.ca <http://www.etsmtl.ca/>Cell. : 514 > 568-9667Email : weidong. [email protected] : lassena.etsmtl.ca > <http://lassena.etsmtl.ca/> > -------------------------------------------------------------------------------------------------------------------------------L’ÉTS > est une constituante du réseau de l’Université du > Québec-------------------------------------------------------------------------------------------------------------Avis: > L'information contenue dans ce courriel est strictement confidentielle. > Toute utilisation par une personne autre que le destinataire est illégale. > Si vous recevez ce courriel par erreur, veuillez svp le détruire et nous en > aviser.-------------------------------------------------------------------------------------------------------------Notice: > The information contained in this message is strictly confidential. Any use > thereof by any person other than the named recipient(s) is illegal. If you > are not the intended recipient please advise sender and delete this > message. <http://www.facebook.com/lassena.etsmtl.ca>* > * <http://www.facebook.com/lassena.etsmtl.ca>* > On 2015-04-12, at 14:03, Moritz Fischer wrote: > > Hi Weidong, > > the XPS project that's made during the current E310 build is not meant > to be used to implement custom designs. > We usually just add stuff to the Makefiles (custom RTL, coregen files, > etc). If you can give us some more info on what you're trying to do, > we'll be able to help you out better. > > Cheers, > > Moritz > > On Sat, Apr 11, 2015 at 10:41 AM, linux > <[email protected]> wrote: > > Hi all, > > > I am actually working on a project needs migrate an old FPGA program to > > E310. First, I want to custom the official FPGA program of E310. But I > found > > some configurations of PS are not the same on the schematics diagram. And I > > tried to export to SDK, but even the simple hello world program didn't > work. > > > I listed what I have done as follow: > > > 1. first, I downloaded the FPGA source code from this address: > > https://github.com/EttusResearch/fpga/tree/master > > > 2. I taped these commands to build the project: > > $source /opt/Xilinx/14.7/ISE_DS/setting64.sh > > $export PATH=$PATH: /opt/Xilinx/14.7/ISE_DS/ISE/bin/bin/lin64/xtclsh > > $cd fpga-master/usrp3/top/e300 > > $make E310 > > > 3. This step took about 1 hour. And then, I open the XPS project. > > $cd build-E310/zynq-ps > > $xps e300_ps.xmp > > > 4. The XPS was just opened. But from here I found some settings I don’t > > understand. In the ZYNQ PS CONFIGURATION, the UART1 was selected using MIO > > 48 … 49, but in the schematic diagram of USRP E300 series Motherboard, the > > UART was using UART0. And UART0 used MIO 14 and MIO 15. > > > 5. If I tried to generate the bitstream from this XPS project, it will give > > me a lot of errors like: > > > ERROR:MapLib:979 - LUT6 symbol > > > > "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I[31]_GND_19_o_add_51_OUT_lut<10>" > > (output > > > signal=axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/Madd_M_AXI_AADDR_I[31]_GND_19_o_add_51_OUT_lut<10>) > > has input signal > > > "axi_interconnect_1/axi_interconnect_1/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT.read_addr_inst/S_AXI_AADDR_Q<10>" > > which will be trimmed. See Section 5 of the Map Report File for details > > about why the input signal will become undriven. > > > 6. Finally, I exported design to SDK with no bitstream, but even the simple > > Hello world print program didn't work. There was nothing output from the > > UART port. > > > I want know if there is someone have done a similar work who can tell me > > where am I doing wrong? > > > > Thanks, > > > Weidong Wang > > > > > > > _______________________________________________ > > Discuss-gnuradio mailing list > > [email protected] > > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > > > >
_______________________________________________ Discuss-gnuradio mailing list [email protected] https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
