As an example, look for issue_stream_command() in uhd/host/lib/usrp/cores/rx_dsp_core_200.cpp
There are separate files to control the various "cores" in the FPGA logic. And, there are multiple versions of things for different boxes, transports, etc. It starts makes sense if you read through a bunch of the code.
- Jeff On 09/08/2015 06:41 PM, Logan Wu wrote:
Hello, I've been tracking the source code to figure out the procedure of transmission/receiving. All I've found out is that the parameters (e.g. freq, gain, etc.) are stored in a property tree, and messages are inserted to the tail of queue. But how does the transmitter/receiver (daughter board) know when to transmit/receive? Specifically, which file in UHD host code does the job of notifying the hardware to transmit/receive? Thank you, Logan
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