> From:         Milos Milosavljevic
> Date:         Sun, 11 Mar 2018 14:36:19 +0000
> Dear All,
> 
> I am using the pfb_clock_sync to estimate the timing offset in my
> QPSK receiver and I have a problem that I would like to ask about.
> 
> Basically if the amplitude of the incoming signal is set relatively
> high (havent checked what actual threshold is) the flowgraph just
> hangs. After the process of elimination I discovered that it is
> actually the pfb_clock_sync block that causes this. Then I put some
> printf statements in the code and found out that the d_k (phase)
> value becomes -NaN when signal amplitude becomes high. The same thing
> is with the d_error from here d_error = (error_i + error_r) / 2.0. 
> 
> I suspect it is due to some filtering (either the RC or diff filter).
> 
> Do you have any suggestions on where this might be coming from?
> 
> Any comments will be highly appreciated.

This sounds like the pfb_clock_sync block is getting a NaN passed in on
the input stream:

        input is NaN => filtered input is NaN => d_error is NaN => d_k is NaN .

Look at your upstream AGC blocks and division blocks as likely culprits
for generating NaNs, since you say "the amplitude of the incoming
signal is set relatively high".


BTW, the small signal, low SNR, Maximum Likelyhood approximation,
Timing Error Detector (TED) used in the pfb_clock_sync block has a
built in assumption that the input amplitude should be noticeably
smaller than +/-1.0 .  Also, for consistent results, you always want to
go into a clock sync block with a controlled signal amplitude.

Regards,
Andy





> 
> Many thanks,
> 
> Kind Regards
> Milos

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