Hi all, After listening to the community’s suggestions, modifying and adding some content, I have completed my final proposal. I am more than happy to work with this community, and I am very grateful to everyone who helped me. I have uploaded the final proposal to Google. Please feel free to review my proposal via GitHub<https://github.com/B0WEN-HU/GSoC-19-Proposal/blob/master/GSoC%202019_%20Cycle-accurate%20Verilog%20Design%20Simulation%20Integration.pdf> or Google Docs<https://docs.google.com/document/d/1sTG9hMINHhwoFnKf96VxbwsOrzd5_BP10qAtQqYYnFI/edit?usp=sharing>. If you have any suggestions, please let me know.
https://github.com/B0WEN-HU/GSoC-19-Proposal/blob/master/GSoC%202019_%20Cycle-accurate%20Verilog%20Design%20Simulation%20Integration.pdf https://docs.google.com/document/d/1sTG9hMINHhwoFnKf96VxbwsOrzd5_BP10qAtQqYYnFI/edit?usp=sharing Thank You, Bowen
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