Hi all, The gr-verilog is an OOT module for GNU Radio integrating Verilog simulation feature. This is the work of GSoC19.
GSoC19 is nearing the end, and I have merged the axi-general branch to master branch. You can find more information in the repository here<https://github.com/B0WEN-HU/gr-verilog> (https://github.com/B0WEN-HU/gr-verilog). Please feel free to try this OOT module. Best regards, Bowen
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