Thanks, Ben, I appreciate your help very much.Is there any documentation or schematic diagram that describes the process that a packet entering the switch's input ports, scheduling, and departing from the switch's output ports? Or there is no such stuff in OVS？ Cheers, Jfhu> Date: Tue, 6 Mar 2012 21:37:32 -0800 > From: [email protected] > To: [email protected] > CC: [email protected] > Subject: Re: [ovs-discuss] Switch architecture of OVS userspace switch > > On Wed, Mar 07, 2012 at 11:35:57AM +0800, HuJingfei wrote: > > > > > > Thanks, Ben, All right. However, at least there is a mapping from the > > software implementation of a switch to its real component. Is that > > right? For example,The struct, dp_netdev, may be mapped to a switch, > > because of following mappings:1. member struct dp_netdev_queue > > queues[N_QUEUES] corresponds to actual buffer of a switch, every > > packet from input ports will enter this buffer first, then will be > > scheduled to go to its destined output port. > > No, that's wrong, that's not at all how these queues are used. These > queues are used to respond to dpif_recv(). Please read the > documentation for that function to obtain more insight. > > > 2. member struct dp_netdev_port *ports[MAX_PORTS] corresponds to > > actual ports of a switch. > > Yes, that is correct. > > > Please correct me if I am wrong. Cheers,Jfhu > > > Date: Tue, 6 Mar 2012 14:17:57 -0800 > > > From: [email protected] > > > To: [email protected] > > > CC: [email protected] > > > Subject: Re: [ovs-discuss] Switch architecture of OVS userspace switch > > > > > > On Tue, Mar 06, 2012 at 11:35:42AM +0800, HuJingfei wrote: > > > > > > > > Hi, all,I'm newbie to OVS. I know there are quite a lot of switch > > > > architectures such as Shared Memory, Shared Medium, Crossbar, Banyan > > > > and so on. Could anyone tell me the userspace OVS switch's > > > > architecture please? Forgive me for my stupid question. Cheers, Jfhu > > > > > > It's a piece of software, not a piece of hardware, so it's not > > > meaningful to try to classify it in terms of hardware designs. > >
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