Il 2015-09-16 12:51 Paul van der Vlis ha scritto:
[...]
There are no drawings involved, as far as I know. Any drawing is an
intermediate object file, thus not important in the overall design
flow.
What I mean are the "sources". I see often the term "Verilog".
Maybe HDL is the correct name.
Verilog and VHDL are languages for describing hardware. They are used to
synthesize hardware in the same way as source code is compiled in object
code.
[...]
My question is in other words, maybe still not perfect: are there ways
to check if a physical object is the working-out of a HDL?
Is there a way to check if object code is working-out of a C++ source
code?
Davide
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