On Fri 09-06-17 13:24:29, Dan Williams wrote:
> With all calls to this routine re-directed through the pmem driver, we can
> kill
> the pmem api indirection. arch_wb_cache_pmem() is now optionally supplied by
> the arch specific asm/pmem.h. Same as before, pmem flushing is only defined
> for x86_64, but it is straightforward to add other archs in the future.
>
> Cc: <[email protected]>
> Cc: Jan Kara <[email protected]>
> Cc: Jeff Moyer <[email protected]>
> Cc: Ingo Molnar <[email protected]>
> Cc: Christoph Hellwig <[email protected]>
> Cc: "H. Peter Anvin" <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Oliver O'Halloran <[email protected]>
> Cc: Matthew Wilcox <[email protected]>
> Cc: Ross Zwisler <[email protected]>
> Signed-off-by: Dan Williams <[email protected]>
Looks good to me. Just one question below...
> -/**
> - * arch_wb_cache_pmem - write back a cache range with CLWB
> - * @vaddr: virtual start address
> - * @size: number of bytes to write back
> - *
> - * Write back a cache range using the CLWB (cache line write back)
> - * instruction. Note that @size is internally rounded up to be cache
> - * line size aligned.
> - */
> static inline void arch_wb_cache_pmem(void *addr, size_t size)
> {
> - u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
> - unsigned long clflush_mask = x86_clflush_size - 1;
> - void *vend = addr + size;
> - void *p;
> -
> - for (p = (void *)((unsigned long)addr & ~clflush_mask);
> - p < vend; p += x86_clflush_size)
> - clwb(p);
> + clean_cache_range(addr,size);
> }
So this will make compilation break on 32-bit x86 as it does not define
clean_cache_range(). Do we somewhere force we are on x86_64 when pmem is
enabled?
Honza
--
Jan Kara <[email protected]>
SUSE Labs, CR
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