Version 3.1.0 of the SMBIOS specification says that the Processor ID field maps to the MIDR register on ARM processors, decode it.
Signed-off-by: Jean Delvare <[email protected]> --- dmidecode.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) --- dmidecode.orig/dmidecode.c 2017-04-05 15:41:00.952972830 +0200 +++ dmidecode/dmidecode.c 2017-04-06 11:27:12.191062872 +0200 @@ -1056,6 +1056,22 @@ static void dmi_processor_id(const struc return; } } + else if ((type >= 0x100 && type <= 0x101) /* ARM */ + || (type >= 0x118 && type <= 0x119)) /* ARM */ + { + u32 midr = DWORD(p); + /* + * The format of this field was not defined for ARM processors + * before version 3.1.0 of the SMBIOS specification, so we + * silently skip it if it reads all zeroes. + */ + if (midr == 0) + return; + printf("%sSignature: Implementor 0x%02x, Variant 0x%x, Architecture %u, Part 0x%03x, Revision %u\n", + prefix, midr >> 24, (midr >> 20) & 0xF, + (midr >> 16) & 0xF, (midr >> 4) & 0xFFF, midr & 0xF); + return; + } else if ((type >= 0x0B && type <= 0x15) /* Intel, Cyrix */ || (type >= 0x28 && type <= 0x2F) /* Intel */ || (type >= 0xA1 && type <= 0xB3) /* Intel */ @@ -1094,7 +1110,7 @@ static void dmi_processor_id(const struc else return; } - else /* not X86-class */ + else /* neither X86 nor ARM */ return; /* -- Jean Delvare SUSE L3 Support _______________________________________________ https://lists.nongnu.org/mailman/listinfo/dmidecode-devel
