Hi all. I am new at Doxygen and I am having trouble to generate the latex
documentation of a VHDL source code. After looking for the same problem at
the mailing list and several attempts I tried with this simple code:
entity test is
port (
in1 : in std_logic;
in2 : in std_logic;
clock : in std_logic;
reset : in std_logic;
out1 : out std_logic);
end test;
architecture rtl of test is
begin -- rtl
and1: process (clock, reset)
begin -- process and
if reset = '0' then -- asynchronous reset (active low)
out1 <= 0;
elsif clock'event and clock = '1' then -- rising clock edge
out1 <= in1 xor in2;
end if;
end process and;
end rtl ;
which, after running the "make" command for the latex generated file
produces the following outpout (from .log file):
"{( {\em \textcolor {vhdlkeyword}{clock}} , } \item [{ {\em \textcolor \ETC.
! Paragraph ended before \\item was complete.
<to be read again>
\par
l.29 ...ttfamily
\mbox{[}Process\mbox{]}}}\hfill}
?
! Extra }, or forgotten \endgroup.
<recently read> }
l.29 ...ttfamily \mbox{[}Process\mbox{]}}}\hfill} ยจ
producing an incomplete .pdf file.
My doxyfile latex related section has the following configuration:
GENERATE_LATEX = YES
LATEX_OUTPUT = latex
LATEX_CMD_NAME = latex
MAKEINDEX_CMD_NAME = makeindex
COMPACT_LATEX = YES
PAPER_TYPE = a4wide
EXTRA_PACKAGES =
LATEX_HEADER =
PDF_HYPERLINKS = YES
USE_PDFLATEX = YES
LATEX_BATCHMODE = NO
LATEX_HIDE_INDICES = NO
LATEX_SOURCE_CODE = YES
Suspecting that the problem was the keyword "process" I commented it and
Latex worked fine. I 've also tried with other VHDL code without processes
and also worked fine.
HTML generation succeded in both cases.
I wonder then if it is a bug of doxygen when dealing with VHDL processes or
I am doing something wrong at the configuration file.
Regards,
Luciano
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