> Is there a way to get Verilog source code parsed by Doxygen? 

With a large delay in my response,
I can provide you with a parser/filter that doxygen can call on verilog-ams
files.

I wrote it in perl and I use it on windows + doxygen 1.6.3;
this may require you to massage it a little for your configuration,
especially if you are a unix user.

I'd like to expand its functionality towards Verilog HDL, so let me know if
you still need it in a private mail.

Cheers, b



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