[PATCH 06/11] drm/amdgpu: Add Fiji support to the DCE 10.0 IP module (v2)

[Alex Deucher]

From: David Zhang <david1.zh...@amd.com>

v2: agd5f: fix up XDMA golden settings

Signed-off-by: David Zhang <david1.zhang at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou at amd.com>
Reviewed-by: Christian K?nig <christian.koenig at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/vi.c        |  7 +++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index a72254a..4b255ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -126,9 +126,31 @@ static const u32 tonga_mgcg_cgcg_init[] =
        mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 };

+static const u32 golden_settings_fiji_a10[] =
+{
+       mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
+       mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
+       mmFBC_MISC, 0x1f311fff, 0x12300000,
+       mmHDMI_CONTROL, 0x31000111, 0x00000011,
+};
+
+static const u32 fiji_mgcg_cgcg_init[] =
+{
+       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
+       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
+};
+
 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
+       case CHIP_FIJI:
+               amdgpu_program_register_sequence(adev,
+                                                fiji_mgcg_cgcg_init,
+                                                (const 
u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_program_register_sequence(adev,
+                                                golden_settings_fiji_a10,
+                                                (const 
u32)ARRAY_SIZE(golden_settings_fiji_a10));
+               break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
@@ -2888,6 +2910,7 @@ static int dce_v10_0_early_init(void *handle)
        dce_v10_0_set_irq_funcs(adev);

        switch (adev->asic_type) {
+       case CHIP_FIJI:
        case CHIP_TONGA:
                adev->mode_info.num_crtc = 6; /* XXX 7??? */
                adev->mode_info.num_hpd = 6;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0788e5c..2550ecf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1199,6 +1199,13 @@ static const struct amdgpu_ip_block_version 
fiji_ip_blocks[] =
                .rev = 0,
                .funcs = &fiji_dpm_ip_funcs,
        },
+       {
+               .type = AMD_IP_BLOCK_TYPE_DCE,
+               .major = 10,
+               .minor = 1,
+               .rev = 0,
+               .funcs = &dce_v10_0_ip_funcs,
+       },
 };

 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
-- 
1.8.3.1