https://bugs.freedesktop.org/show_bug.cgi?id=93826
--- Comment #19 from Alex Deucher <alexdeucher at gmail.com> --- (In reply to Damien from comment #18) > Alex thank you for your return. > > Since my monitor works from scratch with a 7950 or fury but not with three > 290X tested, is that it is possible to retrieve the values that work ? The same algorithm is used on all of those parts. The only reason there would be different dividers selected would be if the pll limits in the vbios or the reference clock were different. However, looking at various vbioses for those different asics indicate that the vbios limits are the same for all of them. I doubt they would be different on your boards. As such. that combination of dividers seems to be disagreeable to your monitor on that specific hw. The underlying hw implementation of the pll varies a bit from asic to asic, so the pll selection probably needs to be tweaked a bit for that hw to be stable at that combination as per comment 17. -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160229/f6b453b2/attachment.html>
