On 10.03.2017 05:32, Sean Paul wrote:
> From: Douglas Anderson <diand...@chromium.org>
>
> The comments in analogix_dp_init_aux() claim that we're disabling aux
> channel retries, but then right below it for Rockchip it sets them to
> 3.  If we actually need 3 retries for Rockchip then we could adjust
> the comment, but it seems more likely that we want the same retry
> behavior across all platforms.
>
> Cc: Stéphane Marchesin <marc...@chromium.org>
> Cc: 征增 王 <w...@rock-chips.com>
> Signed-off-by: Douglas Anderson <diand...@chromium.org>
> Signed-off-by: Sean Paul <seanp...@chromium.org>
> ---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c 
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 29d130222636..57dd1991d7de 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -480,15 +480,16 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
>  
>       analogix_dp_reset_aux(dp);
>  
> -     /* Disable AUX transaction H/W retry */
> +     /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
>       if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
> -             reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
> -                   AUX_HW_RETRY_COUNT_SEL(3) |
> -                   AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +             reg = 0;
>       else
> -             reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
> -                   AUX_HW_RETRY_COUNT_SEL(0) |
> -                   AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +             reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
> +
> +     /* Disable AUX transaction H/W retry */
> +     reg |= AUX_HW_RETRY_COUNT_SEL(0) |
> +            AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +

As I understand you want to disable H/W retry for all. What is the point
in setting retry interval then?
Was it tested on other analogix users (exynos), I mean this patch and
whole patchset?

Regards
Andrzej

>       writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
>  
>       /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */


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