On Sat, 28 Jan 2012 11:07:09 +0100, Jean Delvare <jdelv...@suse.de> wrote: > A udelay value of 20 leads to an I2C bus running at only 25 kbps. I2C > devices can typically operate faster than this, 50 kbps should be fine > for all devices (and compliant devices can always stretch the clock if > needed.) > > FWIW, the vast majority of framebuffer drivers set udelay to 10 > already. So set it to 10 in DRM drivers too, this will make EDID block > reads faster. We might even lower the udelay value later if no problem > is reported.
That runs the DDC at a whopping 50kbps, which is half of the maximum rate specified in the DDC/CI standard. I don't know if we can count on clock stretching (http://www.i2c-bus.org/clock-stretching/), but if so, I don't know why we wouldn't just go to the standard 100kbps data rate and be done with it. Might be nice to see what frequency Windows uses for i2c; anyone want to pull a vga cable apart and hook up a logic analyser? -- keith.pack...@intel.com
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