On 07/08/17 14:47, Laurent Pinchart wrote: > Hi Tomi, > > Thank you for the patch. > > On Tuesday 13 Jun 2017 12:02:10 Tomi Valkeinen wrote: >> 7d267f068a8b4944d52e8b0ae4c8fcc1c1c5c5ba ("drm/omap: work-around for >> errata i886") changed how the PLL dividers and multipliers are >> calculated. While the new way should work fine for all the PLLs, it >> breaks omap5 PLLs. The issues seen are rather odd: seemed that the >> output clock rate is half of what we asked. It is unclear what's causing >> there issues. > > Does this patch result in PLL parameters for half of the expected rate, or > does it compute the expected parameters, with the PLL producing half of the > expected rate for an unknown reason ?
The PLL parameters look fine, and inside the HW limits, afaics, but the produced clock rate seems to be about half. Tomi
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