[PATCH V5 13/25] drm/etnaviv: add HI perf domain

[Christian Gmeiner]

Signed-off-by: Christian Gmeiner <christian.gmei...@gmail.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 55 +++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 
b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
index ba60cb9192c7..f0cdf371663a 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -17,6 +17,7 @@
 
 #include "etnaviv_gpu.h"
 #include "etnaviv_perfmon.h"
+#include "state_hi.xml.h"
 
 struct etnaviv_pm_domain;
 
@@ -31,6 +32,11 @@ struct etnaviv_pm_signal {
 
 struct etnaviv_pm_domain {
        char name[64];
+
+       /* profile register */
+       u32 profile_read;
+       u32 profile_config;
+
        u8 nr_signals;
        const struct etnaviv_pm_signal *signal;
 };
@@ -40,7 +46,56 @@ struct etnaviv_pm_domain_meta {
        u32 nr_domains;
 };
 
+static u32 simple_reg_read(struct etnaviv_gpu *gpu,
+       const struct etnaviv_pm_domain *domain,
+       const struct etnaviv_pm_signal *signal)
+{
+       return gpu_read(gpu, signal->data);
+}
+
+static u32 perf_reg_read(struct etnaviv_gpu *gpu,
+       const struct etnaviv_pm_domain *domain,
+       const struct etnaviv_pm_signal *signal)
+{
+       gpu_write(gpu, domain->profile_config, signal->data);
+
+       return gpu_read(gpu, domain->profile_read);
+}
+
 static const struct etnaviv_pm_domain doms_3d[] = {
+       {
+               .name = "HI",
+               .profile_read = VIVS_MC_PROFILE_HI_READ,
+               .profile_config = VIVS_MC_PROFILE_CONFIG2,
+               .nr_signals = 5,
+               .signal = (const struct etnaviv_pm_signal[]) {
+                       {
+                               "TOTAL_CYCLES",
+                               VIVS_HI_PROFILE_TOTAL_CYCLES,
+                               &simple_reg_read
+                       },
+                       {
+                               "IDLE_CYCLES",
+                               VIVS_HI_PROFILE_IDLE_CYCLES,
+                               &simple_reg_read
+                       },
+                       {
+                               "AXI_CYCLES_READ_REQUEST_STALLED",
+                               
VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
+                               &perf_reg_read
+                       },
+                       {
+                               "AXI_CYCLES_WRITE_REQUEST_STALLED",
+                               
VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
+                               &perf_reg_read
+                       },
+                       {
+                               "AXI_CYCLES_WRITE_DATA_STALLED",
+                               
VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
+                               &perf_reg_read
+                       }
+               }
+       }
 };
 
 static const struct etnaviv_pm_domain doms_2d[] = {
-- 
2.13.5

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