Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx hardware features.
Signed-off-by: Sharat Masetty <smase...@codeaurora.org> --- rnndb/adreno/adreno_pm4.xml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml index 3621f07..c1a82da 100644 --- a/rnndb/adreno/adreno_pm4.xml +++ b/rnndb/adreno/adreno_pm4.xml @@ -288,6 +288,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <!-- switches SMMU pagetable, used on a5xx only --> <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX"/> + <!-- for a6xx --> + <doc>Tells CP the current mode of GPU operation</doc> + <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/> + <doc>Instruct CP to set a few inernal CP registers</doc> + <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/> <!-- pairs of regid and value.. seems to be used to program some TF related regs: -- 1.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
