Am Dienstag, den 05.06.2018, 20:11 +0300 schrieb Leonard Crestez:
> With old bindings imx_gpc_onecell_data always sets num_domains to 2 so
> the DISPMIX domain can't actually be referenced. The pd is still defined
> and pm core shuts it down as "unused" so display can't work.
> 
> Converting to new gpc bindings by adding pgc nodes, also reference
> referencing the newly-defined &pu_disp domain from &lcdif.
> 
> > Signed-off-by: Leonard Crestez <leonard.cres...@nxp.com>
> ---
>  arch/arm/boot/dts/imx6sl.dtsi | 35 ++++++++++++++++++++++++++++++++---
>  1 file changed, 32 insertions(+), 3 deletions(-)
> 
> There are erratas regarding dispmix on 6sl so this might be wrong
> 
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index ab6a7e2e7e8f..9982874fa39e 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -694,14 +694,42 @@
> >                             reg = <0x020dc000 0x4000>;
> >                             interrupt-controller;
> >                             #interrupt-cells = <3>;
> >                             interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
> >                             interrupt-parent = <&intc>;
> > -                           pu-supply = <&reg_pu>;
> > -                           clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
> > -                                    <&clks IMX6SL_CLK_GPU2D_PODF>;
> > +                           clocks = <&clks IMX6SL_CLK_IPG>;
> > +                           clock-names = "ipg";
> >                             #power-domain-cells = <1>;

The above power-domain-cells needs to go away when using the new
binding.

Regards,
Lucas

> +                             pgc {
> > +                                   #address-cells = <1>;
> > +                                   #size-cells = <0>;
> +
> > +                                   power-domain@0 {
> > +                                           reg = <0>;
> > +                                           #power-domain-cells = <0>;
> > +                                   };
> +
> > > +                                 pd_pu: power-domain@1 {
> > +                                           reg = <1>;
> > +                                           #power-domain-cells = <0>;
> > +                                           power-supply = <&reg_pu>;
> > +                                           clocks = <&clks 
> > IMX6SL_CLK_GPU2D_OVG>,
> > +                                                    <&clks 
> > IMX6SL_CLK_GPU2D_PODF>;
> > +                                   };
> +
> > > +                                 pd_disp: power-domain@2 {
> > +                                           reg = <2>;
> > +                                           #power-domain-cells = <0>;
> > +                                           clocks = <&clks IMX6SL_CLK_IPG>,
> > +                                                    <&clks 
> > IMX6SL_CLK_LCDIF_AXI>,
> > +                                                    <&clks 
> > IMX6SL_CLK_LCDIF_PIX>,
> > +                                                    <&clks 
> > IMX6SL_CLK_EPDC_AXI>,
> > +                                                    <&clks 
> > IMX6SL_CLK_EPDC_PIX>,
> > +                                                    <&clks 
> > IMX6SL_CLK_PXP_AXI>;
> > +                                   };
> > +                           };
> >                     };
>  
> > >                   gpr: iomuxc-gpr@20e0000 {
> >                             compatible = "fsl,imx6sl-iomuxc-gpr",
> >                                          "fsl,imx6q-iomuxc-gpr", "syscon";
> @@ -752,10 +780,11 @@
> >                             clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
> >                                      <&clks IMX6SL_CLK_LCDIF_AXI>,
> >                                      <&clks IMX6SL_CLK_DUMMY>;
> >                             clock-names = "pix", "axi", "disp_axi";
> >                             status = "disabled";
> > +                           power-domains = <&pd_disp>;
> >                     };
>  
> > >                   dcp: dcp@20fc000 {
> >                             compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
> >                             reg = <0x020fc000 0x4000>;
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