Quoting spa...@codeaurora.org (2018-06-05 21:50:16) > On 2018-06-05 20:50, Rob Herring wrote: > > On Tue, Jun 05, 2018 at 11:10:16AM +0530, Sandeep Panda wrote: > >> Document the bindings used for the sn65dsi86 DSI to eDP bridge. [...] > >> and > >> + the second cell is used to specify flags. > >> + See ../../gpio/gpio.txt for more information. > >> +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description > >> of > >> + the cell formats. > >> + > >> +- clock-names: should be "refclk" > >> +- clocks: Specification for input reference clock. The reference > >> + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. > >> + > >> +- lane-mapping: Specification to describe the logical to physical > >> lane > > > > As I mentioned in v7, we already have a property for this. It's called > > 'data-lanes' and defined in media/video-interfaces.txt. Use that. If > > you > > need polarity too, then add a property for that. And add it to > > video-interfaces.txt. > > The data-lanes property mentioned in media/video-interfaces.txt is > referring > to DSI/CSI lanes where assumption is clock lane is fixed at index 0. But > here > the we want to mention about eDP lanes which do not have dedicated clock > lane. > So can we still use the existing data-lanes property here?
Why is that a problem? It's just a property name. There are data-lanes and clock-lanes properties in the video-interfaces.txt file by the way. It would be nice if that document could be updated for displayport and DSI (e.g. clock-noncontinuous or link-frequencies) or even just mention in there that these can apply to DSI and displayport too. _______________________________________________ dri-devel mailing list email@example.com https://lists.freedesktop.org/mailman/listinfo/dri-devel