On Tue, Aug 28, 2018 at 05:40:03PM -0700, Jeykumar Sankaran wrote:
> Support for CDM block is not present in DPU. Remove CDM
> handlers from resource manager.
I think there's some leftovers that can be cleaned up...
$ ack -i cdm
disp/dpu1/dpu_hw_mdss.h
103: DPU_HW_BLK_CDM,
192:enum dpu_cdm {
193: CDM_0 = 1,
194: CDM_1,
195: CDM_MAX
454:#define DPU_DBG_MASK_CDM (1 << 1)
disp/dpu1/dpu_hw_catalog.h
533: * struct dpu_cdm_cfg - information of chroma down blocks
537: * @intf_connect Bitmask of INTF IDs this CDM can connect to
539:struct dpu_cdm_cfg {
737: u32 cdm_count;
738: struct dpu_cdm_cfg *cdm;
776:#define BLK_CDM(s) ((s)->cdm)
disp/dpu1/dpu_hw_catalog.c
324: * CDM sub blocks config
326:static struct dpu_cdm_cfg sdm845_cdm[] = {
328: .name = "cdm_0", .id = CDM_0,
461: .cdm_count = ARRAY_SIZE(sdm845_cdm),
462: .cdm = sdm845_cdm,
>
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/Makefile | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323
> -----------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 ----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 14 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 17 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 68 +----
> drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 4 -
> 11 files changed, 2 insertions(+), 593 deletions(-)
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 261fa79..19ab521 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -58,7 +58,6 @@ msm-y := \
> disp/dpu1/dpu_formats.o \
> disp/dpu1/dpu_hw_blk.o \
> disp/dpu1/dpu_hw_catalog.o \
> - disp/dpu1/dpu_hw_cdm.o \
> disp/dpu1/dpu_hw_ctl.o \
> disp/dpu1/dpu_hw_interrupts.o \
> disp/dpu1/dpu_hw_intf.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index e453271..e844afa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -32,11 +32,9 @@
> /**
> * Encoder functions and data types
> * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
> - * @needs_cdm: Encoder requests a CDM based on pixel format conversion
> needs
> */
> struct dpu_encoder_hw_resources {
> enum dpu_intf_mode intfs[INTF_MAX];
> - bool needs_cdm;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index b5fc65c..f796683 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -22,7 +22,6 @@
> #include "dpu_hw_pingpong.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_top.h"
> -#include "dpu_hw_cdm.h"
> #include "dpu_encoder.h"
> #include "dpu_crtc.h"
>
> @@ -205,8 +204,6 @@ struct dpu_encoder_irq {
> * @parent_ops: Callbacks exposed by the parent to the phys_enc
> * @hw_mdptop: Hardware interface to the top registers
> * @hw_ctl: Hardware interface to the ctl registers
> - * @hw_cdm: Hardware interface to the cdm registers
> - * @cdm_cfg: Chroma-down hardware configuration
> * @hw_pp: Hardware interface to the ping pong registers
> * @dpu_kms: Pointer to the dpu_kms top level
> * @cached_mode: DRM mode cached at mode_set time, acted on in enable
> @@ -235,8 +232,6 @@ struct dpu_encoder_phys {
> const struct dpu_encoder_virt_ops *parent_ops;
> struct dpu_hw_mdp *hw_mdptop;
> struct dpu_hw_ctl *hw_ctl;
> - struct dpu_hw_cdm *hw_cdm;
> - struct dpu_hw_cdm_cfg cdm_cfg;
> struct dpu_hw_pingpong *hw_pp;
> struct dpu_kms *dpu_kms;
> struct drm_display_mode cached_mode;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> deleted file mode 100644
> index 554874b..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> +++ /dev/null
> @@ -1,323 +0,0 @@
> -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hwio.h"
> -#include "dpu_hw_catalog.h"
> -#include "dpu_hw_cdm.h"
> -#include "dpu_dbg.h"
> -#include "dpu_kms.h"
> -
> -#define CDM_CSC_10_OPMODE 0x000
> -#define CDM_CSC_10_BASE 0x004
> -
> -#define CDM_CDWN2_OP_MODE 0x100
> -#define CDM_CDWN2_CLAMP_OUT 0x104
> -#define CDM_CDWN2_PARAMS_3D_0 0x108
> -#define CDM_CDWN2_PARAMS_3D_1 0x10C
> -#define CDM_CDWN2_COEFF_COSITE_H_0 0x110
> -#define CDM_CDWN2_COEFF_COSITE_H_1 0x114
> -#define CDM_CDWN2_COEFF_COSITE_H_2 0x118
> -#define CDM_CDWN2_COEFF_OFFSITE_H_0 0x11C
> -#define CDM_CDWN2_COEFF_OFFSITE_H_1 0x120
> -#define CDM_CDWN2_COEFF_OFFSITE_H_2 0x124
> -#define CDM_CDWN2_COEFF_COSITE_V 0x128
> -#define CDM_CDWN2_COEFF_OFFSITE_V 0x12C
> -#define CDM_CDWN2_OUT_SIZE 0x130
> -
> -#define CDM_HDMI_PACK_OP_MODE 0x200
> -#define CDM_CSC_10_MATRIX_COEFF_0 0x004
> -
> -/**
> - * Horizontal coefficients for cosite chroma downscale
> - * s13 representation of coefficients
> - */
> -static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
> -
> -/**
> - * Horizontal coefficients for offsite chroma downscale
> - */
> -static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
> -
> -/**
> - * Vertical coefficients for cosite chroma downscale
> - */
> -static u32 cosite_v_coeff[] = {0x00080004};
> -/**
> - * Vertical coefficients for offsite chroma downscale
> - */
> -static u32 offsite_v_coeff[] = {0x00060002};
> -
> -/* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module
> */
> -static struct dpu_csc_cfg rgb2yuv_cfg = {
> - {
> - 0x0083, 0x0102, 0x0032,
> - 0x1fb5, 0x1f6c, 0x00e1,
> - 0x00e1, 0x1f45, 0x1fdc
> - },
> - { 0x00, 0x00, 0x00 },
> - { 0x0040, 0x0200, 0x0200 },
> - { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
> - { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
> -};
> -
> -static struct dpu_cdm_cfg *_cdm_offset(enum dpu_cdm cdm,
> - struct dpu_mdss_cfg *m,
> - void __iomem *addr,
> - struct dpu_hw_blk_reg_map *b)
> -{
> - int i;
> -
> - for (i = 0; i < m->cdm_count; i++) {
> - if (cdm == m->cdm[i].id) {
> - b->base_off = addr;
> - b->blk_off = m->cdm[i].base;
> - b->length = m->cdm[i].len;
> - b->hwversion = m->hwversion;
> - b->log_mask = DPU_DBG_MASK_CDM;
> - return &m->cdm[i];
> - }
> - }
> -
> - return ERR_PTR(-EINVAL);
> -}
> -
> -static int dpu_hw_cdm_setup_csc_10bit(struct dpu_hw_cdm *ctx,
> - struct dpu_csc_cfg *data)
> -{
> - dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true);
> -
> - return 0;
> -}
> -
> -static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx,
> - struct dpu_hw_cdm_cfg *cfg)
> -{
> - struct dpu_hw_blk_reg_map *c = &ctx->hw;
> - u32 opmode = 0;
> - u32 out_size = 0;
> -
> - if (cfg->output_bit_depth == CDM_CDWN_OUTPUT_10BIT)
> - opmode &= ~BIT(7);
> - else
> - opmode |= BIT(7);
> -
> - /* ENABLE DWNS_H bit */
> - opmode |= BIT(1);
> -
> - switch (cfg->h_cdwn_type) {
> - case CDM_CDWN_DISABLE:
> - /* CLEAR METHOD_H field */
> - opmode &= ~(0x18);
> - /* CLEAR DWNS_H bit */
> - opmode &= ~BIT(1);
> - break;
> - case CDM_CDWN_PIXEL_DROP:
> - /* Clear METHOD_H field (pixel drop is 0) */
> - opmode &= ~(0x18);
> - break;
> - case CDM_CDWN_AVG:
> - /* Clear METHOD_H field (Average is 0x1) */
> - opmode &= ~(0x18);
> - opmode |= (0x1 << 0x3);
> - break;
> - case CDM_CDWN_COSITE:
> - /* Clear METHOD_H field (Average is 0x2) */
> - opmode &= ~(0x18);
> - opmode |= (0x2 << 0x3);
> - /* Co-site horizontal coefficients */
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
> - cosite_h_coeff[0]);
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
> - cosite_h_coeff[1]);
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
> - cosite_h_coeff[2]);
> - break;
> - case CDM_CDWN_OFFSITE:
> - /* Clear METHOD_H field (Average is 0x3) */
> - opmode &= ~(0x18);
> - opmode |= (0x3 << 0x3);
> -
> - /* Off-site horizontal coefficients */
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
> - offsite_h_coeff[0]);
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
> - offsite_h_coeff[1]);
> - DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
> - offsite_h_coeff[2]);
> - break;
> - default:
> - pr_err("%s invalid horz down sampling type\n", __func__);
> - return -EINVAL;
> - }
> -
> - /* ENABLE DWNS_V bit */
> - opmode |= BIT(2);
> -
> - switch (cfg->v_cdwn_type) {
> - case CDM_CDWN_DISABLE:
> - /* CLEAR METHOD_V field */
> - opmode &= ~(0x60);
> - /* CLEAR DWNS_V bit */
> - opmode &= ~BIT(2);
> - break;
> - case CDM_CDWN_PIXEL_DROP:
> - /* Clear METHOD_V field (pixel drop is 0) */
> - opmode &= ~(0x60);
> - break;
> - case CDM_CDWN_AVG:
> - /* Clear METHOD_V field (Average is 0x1) */
> - opmode &= ~(0x60);
> - opmode |= (0x1 << 0x5);
> - break;
> - case CDM_CDWN_COSITE:
> - /* Clear METHOD_V field (Average is 0x2) */
> - opmode &= ~(0x60);
> - opmode |= (0x2 << 0x5);
> - /* Co-site vertical coefficients */
> - DPU_REG_WRITE(c,
> - CDM_CDWN2_COEFF_COSITE_V,
> - cosite_v_coeff[0]);
> - break;
> - case CDM_CDWN_OFFSITE:
> - /* Clear METHOD_V field (Average is 0x3) */
> - opmode &= ~(0x60);
> - opmode |= (0x3 << 0x5);
> -
> - /* Off-site vertical coefficients */
> - DPU_REG_WRITE(c,
> - CDM_CDWN2_COEFF_OFFSITE_V,
> - offsite_v_coeff[0]);
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - if (cfg->v_cdwn_type || cfg->h_cdwn_type)
> - opmode |= BIT(0); /* EN CDWN module */
> - else
> - opmode &= ~BIT(0);
> -
> - out_size = (cfg->output_width & 0xFFFF) |
> - ((cfg->output_height & 0xFFFF) << 16);
> - DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
> - DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
> - DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT,
> - ((0x3FF << 16) | 0x0));
> -
> - return 0;
> -}
> -
> -static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
> - struct dpu_hw_cdm_cfg *cdm)
> -{
> - struct dpu_hw_blk_reg_map *c = &ctx->hw;
> - const struct dpu_format *fmt = cdm->output_fmt;
> - struct cdm_output_cfg cdm_cfg = { 0 };
> - u32 opmode = 0;
> - u32 csc = 0;
> -
> - if (!DPU_FORMAT_IS_YUV(fmt))
> - return -EINVAL;
> -
> - if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
> - if (fmt->chroma_sample != DPU_CHROMA_H1V2)
> - return -EINVAL; /*unsupported format */
> - opmode = BIT(0);
> - opmode |= (fmt->chroma_sample << 1);
> - cdm_cfg.intf_en = true;
> - }
> -
> - csc |= BIT(2);
> - csc &= ~BIT(1);
> - csc |= BIT(0);
> -
> - if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
> - ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
> -
> - DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
> - DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
> - return 0;
> -}
> -
> -static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
> -{
> - struct cdm_output_cfg cdm_cfg = { 0 };
> -
> - if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
> - ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
> -}
> -
> -static void _setup_cdm_ops(struct dpu_hw_cdm_ops *ops,
> - unsigned long features)
> -{
> - ops->setup_csc_data = dpu_hw_cdm_setup_csc_10bit;
> - ops->setup_cdwn = dpu_hw_cdm_setup_cdwn;
> - ops->enable = dpu_hw_cdm_enable;
> - ops->disable = dpu_hw_cdm_disable;
> -}
> -
> -static struct dpu_hw_blk_ops dpu_hw_ops = {
> - .start = NULL,
> - .stop = NULL,
> -};
> -
> -struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
> - void __iomem *addr,
> - struct dpu_mdss_cfg *m,
> - struct dpu_hw_mdp *hw_mdp)
> -{
> - struct dpu_hw_cdm *c;
> - struct dpu_cdm_cfg *cfg;
> - int rc;
> -
> - c = kzalloc(sizeof(*c), GFP_KERNEL);
> - if (!c)
> - return ERR_PTR(-ENOMEM);
> -
> - cfg = _cdm_offset(idx, m, addr, &c->hw);
> - if (IS_ERR_OR_NULL(cfg)) {
> - kfree(c);
> - return ERR_PTR(-EINVAL);
> - }
> -
> - c->idx = idx;
> - c->caps = cfg;
> - _setup_cdm_ops(&c->ops, c->caps->features);
> - c->hw_mdp = hw_mdp;
> -
> - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CDM, idx, &dpu_hw_ops);
> - if (rc) {
> - DPU_ERROR("failed to init hw blk %d\n", rc);
> - goto blk_init_error;
> - }
> -
> - /*
> - * Perform any default initialization for the chroma down module
> - * @setup default csc coefficients
> - */
> - dpu_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
> -
> - return c;
> -
> -blk_init_error:
> - kzfree(c);
> -
> - return ERR_PTR(rc);
> -}
> -
> -void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm)
> -{
> - if (cdm)
> - dpu_hw_blk_destroy(&cdm->base);
> - kfree(cdm);
> -}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> deleted file mode 100644
> index 5cceb1e..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> +++ /dev/null
> @@ -1,139 +0,0 @@
> -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef _DPU_HW_CDM_H
> -#define _DPU_HW_CDM_H
> -
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hw_top.h"
> -#include "dpu_hw_blk.h"
> -
> -struct dpu_hw_cdm;
> -
> -struct dpu_hw_cdm_cfg {
> - u32 output_width;
> - u32 output_height;
> - u32 output_bit_depth;
> - u32 h_cdwn_type;
> - u32 v_cdwn_type;
> - const struct dpu_format *output_fmt;
> - u32 output_type;
> - int flags;
> -};
> -
> -enum dpu_hw_cdwn_type {
> - CDM_CDWN_DISABLE,
> - CDM_CDWN_PIXEL_DROP,
> - CDM_CDWN_AVG,
> - CDM_CDWN_COSITE,
> - CDM_CDWN_OFFSITE,
> -};
> -
> -enum dpu_hw_cdwn_output_type {
> - CDM_CDWN_OUTPUT_HDMI,
> - CDM_CDWN_OUTPUT_WB,
> -};
> -
> -enum dpu_hw_cdwn_output_bit_depth {
> - CDM_CDWN_OUTPUT_8BIT,
> - CDM_CDWN_OUTPUT_10BIT,
> -};
> -
> -/**
> - * struct dpu_hw_cdm_ops : Interface to the chroma down Hw driver functions
> - * Assumption is these functions will be called after
> - * clocks are enabled
> - * @setup_csc: Programs the csc matrix
> - * @setup_cdwn: Sets up the chroma down sub module
> - * @enable: Enables the output to interface and programs the
> - * output packer
> - * @disable: Puts the cdm in bypass mode
> - */
> -struct dpu_hw_cdm_ops {
> - /**
> - * Programs the CSC matrix for conversion from RGB space to YUV space,
> - * it is optional to call this function as this matrix is automatically
> - * set during initialization, user should call this if it wants
> - * to program a different matrix than default matrix.
> - * @cdm: Pointer to the chroma down context structure
> - * @data Pointer to CSC configuration data
> - * return: 0 if success; error code otherwise
> - */
> - int (*setup_csc_data)(struct dpu_hw_cdm *cdm,
> - struct dpu_csc_cfg *data);
> -
> - /**
> - * Programs the Chroma downsample part.
> - * @cdm Pointer to chroma down context
> - */
> - int (*setup_cdwn)(struct dpu_hw_cdm *cdm,
> - struct dpu_hw_cdm_cfg *cfg);
> -
> - /**
> - * Enable the CDM module
> - * @cdm Pointer to chroma down context
> - */
> - int (*enable)(struct dpu_hw_cdm *cdm,
> - struct dpu_hw_cdm_cfg *cfg);
> -
> - /**
> - * Disable the CDM module
> - * @cdm Pointer to chroma down context
> - */
> - void (*disable)(struct dpu_hw_cdm *cdm);
> -};
> -
> -struct dpu_hw_cdm {
> - struct dpu_hw_blk base;
> - struct dpu_hw_blk_reg_map hw;
> -
> - /* chroma down */
> - const struct dpu_cdm_cfg *caps;
> - enum dpu_cdm idx;
> -
> - /* mdp top hw driver */
> - struct dpu_hw_mdp *hw_mdp;
> -
> - /* ops */
> - struct dpu_hw_cdm_ops ops;
> -};
> -
> -/**
> - * dpu_hw_cdm - convert base object dpu_hw_base to container
> - * @hw: Pointer to base hardware block
> - * return: Pointer to hardware block container
> - */
> -static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)
> -{
> - return container_of(hw, struct dpu_hw_cdm, base);
> -}
> -
> -/**
> - * dpu_hw_cdm_init - initializes the cdm hw driver object.
> - * should be called once before accessing every cdm.
> - * @idx: cdm index for which driver object is required
> - * @addr: mapped register io address of MDP
> - * @m : pointer to mdss catalog data
> - * @hw_mdp: pointer to mdp top hw driver object
> - */
> -struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
> - void __iomem *addr,
> - struct dpu_mdss_cfg *m,
> - struct dpu_hw_mdp *hw_mdp);
> -
> -/**
> - * dpu_hw_cdm_destroy - destroys CDM driver context
> - * @cdm: pointer to CDM driver context
> - */
> -void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm);
> -
> -#endif /*_DPU_HW_CDM_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 06be7cf..b394a18 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -224,19 +224,6 @@ static inline int dpu_hw_ctl_get_bitmask_intf(struct
> dpu_hw_ctl *ctx,
> return 0;
> }
>
> -static inline int dpu_hw_ctl_get_bitmask_cdm(struct dpu_hw_ctl *ctx,
> - u32 *flushbits, enum dpu_cdm cdm)
> -{
> - switch (cdm) {
> - case CDM_0:
> - *flushbits |= BIT(26);
> - break;
> - default:
> - return -EINVAL;
> - }
> - return 0;
> -}
> -
> static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32
> timeout_us)
> {
> struct dpu_hw_blk_reg_map *c = &ctx->hw;
> @@ -485,7 +472,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
> ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
> ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
> - ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
> };
>
> static struct dpu_hw_blk_ops dpu_hw_ops = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index c66a71f..6f313fa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -142,10 +142,6 @@ struct dpu_hw_ctl_ops {
> u32 *flushbits,
> enum dpu_intf blk);
>
> - int (*get_bitmask_cdm)(struct dpu_hw_ctl *ctx,
> - u32 *flushbits,
> - enum dpu_cdm blk);
> -
> /**
> * Set all blend stages to disabled
> * @ctx : ctl path ctx pointer
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index db2798e..b878125 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -98,23 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
> DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
> }
>
> -static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
> - struct cdm_output_cfg *cfg)
> -{
> - struct dpu_hw_blk_reg_map *c;
> - u32 out_ctl = 0;
> -
> - if (!mdp || !cfg)
> - return;
> -
> - c = &mdp->hw;
> -
> - if (cfg->intf_en)
> - out_ctl |= BIT(19);
> -
> - DPU_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
> -}
> -
> static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
> enum dpu_clk_ctrl_type clk_ctrl, bool enable)
> {
> @@ -307,7 +290,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> unsigned long cap)
> {
> ops->setup_split_pipe = dpu_hw_setup_split_pipe;
> - ops->setup_cdm_output = dpu_hw_setup_cdm_output;
> ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
> ops->get_danger_status = dpu_hw_get_danger_status;
> ops->setup_vsync_source = dpu_hw_setup_vsync_source;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> index 899925a..192e338 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> @@ -52,14 +52,6 @@ struct split_pipe_cfg {
> };
>
> /**
> - * struct cdm_output_cfg: output configuration for cdm
> - * @intf_en : enable/disable interface output
> - */
> -struct cdm_output_cfg {
> - bool intf_en;
> -};
> -
> -/**
> * struct dpu_danger_safe_status: danger and safe status signals
> * @mdp: top level status
> * @sspp: source pipe status
> @@ -89,7 +81,6 @@ struct dpu_vsync_source_cfg {
> * Assumption is these functions will be called after clocks are enabled.
> * @setup_split_pipe : Programs the pipe control registers
> * @setup_pp_split : Programs the pp split control registers
> - * @setup_cdm_output : programs cdm control
> * @setup_traffic_shaper : programs traffic shaper control
> */
> struct dpu_hw_mdp_ops {
> @@ -102,14 +93,6 @@ struct dpu_hw_mdp_ops {
> struct split_pipe_cfg *p);
>
> /**
> - * setup_cdm_output() : Setup selection control of the cdm data path
> - * @mdp : mdp top context driver
> - * @cfg : cdm output configuration
> - */
> - void (*setup_cdm_output)(struct dpu_hw_mdp *mdp,
> - struct cdm_output_cfg *cfg);
> -
> - /**
> * setup_traffic_shaper() : Setup traffic shaper control
> * @mdp : mdp top context driver
> * @cfg : traffic shaper configuration
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 388ae65..e08b3bd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -16,7 +16,6 @@
> #include "dpu_kms.h"
> #include "dpu_hw_lm.h"
> #include "dpu_hw_ctl.h"
> -#include "dpu_hw_cdm.h"
> #include "dpu_hw_pingpong.h"
> #include "dpu_hw_intf.h"
> #include "dpu_encoder.h"
> @@ -214,9 +213,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type,
> void *hw)
> case DPU_HW_BLK_CTL:
> dpu_hw_ctl_destroy(hw);
> break;
> - case DPU_HW_BLK_CDM:
> - dpu_hw_cdm_destroy(hw);
> - break;
> case DPU_HW_BLK_PINGPONG:
> dpu_hw_pingpong_destroy(hw);
> break;
> @@ -290,9 +286,6 @@ static int _dpu_rm_hw_blk_create(
> case DPU_HW_BLK_CTL:
> hw = dpu_hw_ctl_init(id, mmio, cat);
> break;
> - case DPU_HW_BLK_CDM:
> - hw = dpu_hw_cdm_init(id, mmio, cat, hw_mdp);
> - break;
> case DPU_HW_BLK_PINGPONG:
> hw = dpu_hw_pingpong_init(id, mmio, cat);
> break;
> @@ -423,15 +416,6 @@ int dpu_rm_init(struct dpu_rm *rm,
> }
> }
>
> - for (i = 0; i < cat->cdm_count; i++) {
> - rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_CDM,
> - cat->cdm[i].id, &cat->cdm[i]);
> - if (rc) {
> - DPU_ERROR("failed: cdm hw not available\n");
> - goto fail;
> - }
> - }
> -
> return 0;
>
> fail:
> @@ -628,55 +612,11 @@ static int _dpu_rm_reserve_ctls(
> return 0;
> }
>
> -static int _dpu_rm_reserve_cdm(
> - struct dpu_rm *rm,
> - struct dpu_rm_rsvp *rsvp,
> - uint32_t id,
> - enum dpu_hw_blk_type type)
> -{
> - struct dpu_rm_hw_iter iter;
> -
> - DRM_DEBUG_KMS("type %d id %d\n", type, id);
> -
> - dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM);
> - while (_dpu_rm_get_hw_locked(rm, &iter)) {
> - const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
> - const struct dpu_cdm_cfg *caps = cdm->caps;
> - bool match = false;
> -
> - if (RESERVED_BY_OTHER(iter.blk, rsvp))
> - continue;
> -
> - if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
> - match = test_bit(id, &caps->intf_connect);
> -
> - DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
> - iter.blk->type, iter.blk->id, rsvp->enc_id,
> - caps->intf_connect, match);
> -
> - if (!match)
> - continue;
> -
> - trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
> - rsvp->enc_id);
> - iter.blk->rsvp_nxt = rsvp;
> - break;
> - }
> -
> - if (!iter.hw) {
> - DPU_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
> - return -ENAVAIL;
> - }
> -
> - return 0;
> -}
> -
> static int _dpu_rm_reserve_intf(
> struct dpu_rm *rm,
> struct dpu_rm_rsvp *rsvp,
> uint32_t id,
> - enum dpu_hw_blk_type type,
> - bool needs_cdm)
> + enum dpu_hw_blk_type type)
> {
> struct dpu_rm_hw_iter iter;
> int ret = 0;
> @@ -704,9 +644,6 @@ static int _dpu_rm_reserve_intf(
> return -EINVAL;
> }
>
> - if (needs_cdm)
> - ret = _dpu_rm_reserve_cdm(rm, rsvp, id, type);
> -
> return ret;
> }
>
> @@ -723,7 +660,7 @@ static int _dpu_rm_reserve_intf_related_hw(
> continue;
> id = i + INTF_0;
> ret = _dpu_rm_reserve_intf(rm, rsvp, id,
> - DPU_HW_BLK_INTF, hw_res->needs_cdm);
> + DPU_HW_BLK_INTF);
> if (ret)
> return ret;
> }
> @@ -769,7 +706,6 @@ static int _dpu_rm_make_next_rsvp(
> return ret;
> }
>
> - /* Assign INTFs and blks whose usage is tied to them: CTL & CDM */
> ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index ae0ca50..0be51db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -868,10 +868,6 @@
> TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
> __entry->enc_id)
> );
> -DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_cdm,
> - TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> - TP_ARGS(id, type, enc_id)
> -);
> DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
> TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> TP_ARGS(id, type, enc_id)
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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