On Thu, Jun 14, 2018 at 09:01:10PM -0700, Abhinav Kumar wrote: > Currenty the VCO rate in the 10nm PLL driver relies > on the parent rate which is not configured. > > Configure the VCO rate to 19.2 Mhz as required by > the 10nm PLL driver. > > Signed-off-by: Abhinav Kumar <[email protected]>
Sorry for missing this when it was posted. This is consistent with the other files in pll/, so Reviewed-by: Sean Paul <[email protected]> I'll stuff this in dpu-staging/for-next. Sean > --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > index c4c37a7..fb485cb 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > @@ -39,6 +39,8 @@ > #define DSI_PIXEL_PLL_CLK 1 > #define NUM_PROVIDED_CLKS 2 > > +#define VCO_REF_CLK_RATE 19200000 > + > struct dsi_pll_regs { > u32 pll_prop_gain_rate; > u32 pll_lockdet_rate; > @@ -316,7 +318,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, > unsigned long rate, > parent_rate); > > pll_10nm->vco_current_rate = rate; > - pll_10nm->vco_ref_clk_rate = parent_rate; > + pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; > > dsi_pll_setup_config(pll_10nm); > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
