[PATCH v4 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT

[Matthias Kaehlcke]

Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.

Signed-off-by: Matthias Kaehlcke <m...@chromium.org>
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
  storing it in a struct field
- updated commit message

Changes in v3:
- use default name and rate if the ref clock is not specified
  in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE

Changes in v2:
- patch added to the series
---
 .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c   | 24 +++++++++++++++----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..76e5188169b91 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
 
 #define NUM_PROVIDED_CLKS      2
 
-#define VCO_REF_CLK_RATE       27000000
 #define VCO_MIN_RATE           600000000
 #define VCO_MAX_RATE           1200000000
 
@@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, 
unsigned long rate,
        DBG("rate=%lu, parent's=%lu", rate, parent_rate);
 
        temp = rate / 10;
-       val = VCO_REF_CLK_RATE / 10;
+       val = parent_rate / 10;
        fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
        fb_divider = fb_divider / 2 - 1;
        pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
                                        pll_28nm->clks, pll_28nm->num_clks);
 }
 
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+                            const char *ref_clk_name)
 {
        char *clk_name, *parent_name, *vco_name;
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "pxo" },
+               .parent_names = &ref_clk_name,
                .num_parents = 1,
                .flags = CLK_IGNORE_UNUSED,
                .ops = &clk_ops_dsi_pll_28nm_vco,
@@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct 
platform_device *pdev,
 {
        struct dsi_pll_28nm *pll_28nm;
        struct msm_dsi_pll *pll;
+       struct clk *vco_ref_clk;
+       const char *vco_ref_clk_name;
        int ret;
 
        if (!pdev)
@@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct 
platform_device *pdev,
        pll_28nm->pdev = pdev;
        pll_28nm->id = id + 1;
 
+       vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+       if (!IS_ERR(vco_ref_clk)) {
+               vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+       } else {
+               ret = PTR_ERR(vco_ref_clk);
+               if (ret == -EPROBE_DEFER)
+                       return ERR_PTR(ret);
+
+               dev_warn(&pdev->dev, "'ref' clock is not specified, using 
default name\n");
+               vco_ref_clk_name = "pxo";
+       }
+
        pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
        if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
                dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
@@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct 
platform_device *pdev,
        pll->en_seq_cnt = 1;
        pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
 
-       ret = pll_28nm_register(pll_28nm);
+       ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
        if (ret) {
                dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
                return ERR_PTR(ret);
-- 
2.20.0.rc1.387.gf8505762e3-goog

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