tree: git://people.freedesktop.org/~agd5f/linux.git amd-18.50
head: 88a0039cb034176ee3416dd0c3a49feea2f446ab
commit: a26f88704ef76f0213692b3b04f210de6e9e8676 [1284/1415] drm/scheduler: fix
build error due to change in scheduler struct
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout a26f88704ef76f0213692b3b04f210de6e9e8676
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
In file included from include/linux/swab.h:5:0,
from arch/arm/include/asm/opcodes.h:89,
from arch/arm/include/asm/bug.h:7,
from include/linux/bug.h:5,
from include/linux/thread_info.h:12,
from include/asm-generic/current.h:5,
from ./arch/arm/include/generated/asm/current.h:1,
from include/linux/sched.h:12,
from include/linux/kthread.h:6,
from drivers/gpu/drm/v3d/v3d_sched.c:21:
drivers/gpu/drm/v3d/v3d_sched.c: In function 'v3d_job_timedout':
>> drivers/gpu/drm/v3d/v3d_sched.c:157:44: error: 'job_q' undeclared (first use
>> in this function); did you mean 'job'?
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^
include/uapi/linux/swab.h:114:54: note: in definition of macro '__swab32'
#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
^
include/linux/byteorder/generic.h:89:21: note: in expansion of macro
'__le32_to_cpu'
#define le32_to_cpu __le32_to_cpu
^~~~~~~~~~~~~
>> arch/arm/include/asm/io.h:310:32: note: in expansion of macro 'readl_relaxed'
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_drv.h:166:37: note: in expansion of macro 'readl'
#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
^~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:157:13: note: in expansion of macro
>> 'V3D_CORE_READ'
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:157:30: note: in expansion of macro
>> 'V3D_CLE_CTNCA'
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^~~~~~~~~~~~~
drivers/gpu/drm/v3d/v3d_sched.c:157:44: note: each undeclared identifier is
reported only once for each function it appears in
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^
include/uapi/linux/swab.h:114:54: note: in definition of macro '__swab32'
#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
^
include/linux/byteorder/generic.h:89:21: note: in expansion of macro
'__le32_to_cpu'
#define le32_to_cpu __le32_to_cpu
^~~~~~~~~~~~~
>> arch/arm/include/asm/io.h:310:32: note: in expansion of macro 'readl_relaxed'
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_drv.h:166:37: note: in expansion of macro 'readl'
#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
^~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:157:13: note: in expansion of macro
>> 'V3D_CORE_READ'
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:157:30: note: in expansion of macro
>> 'V3D_CLE_CTNCA'
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:158:30: error: implicit declaration of
>> function 'V3D_CLE_CTNRA'; did you mean 'V3D_CLE_CTNCA'?
>> [-Werror=implicit-function-declaration]
u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
^
include/uapi/linux/swab.h:114:54: note: in definition of macro '__swab32'
#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
^
include/linux/byteorder/generic.h:89:21: note: in expansion of macro
'__le32_to_cpu'
#define le32_to_cpu __le32_to_cpu
^~~~~~~~~~~~~
>> arch/arm/include/asm/io.h:310:32: note: in expansion of macro 'readl_relaxed'
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_drv.h:166:37: note: in expansion of macro 'readl'
#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
^~~~~
drivers/gpu/drm/v3d/v3d_sched.c:158:13: note: in expansion of macro
'V3D_CORE_READ'
u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
^~~~~~~~~~~~~
>> drivers/gpu/drm/v3d/v3d_sched.c:166:9: error: 'struct v3d_job' has no member
>> named 'timedout_ctca'
if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
^~
>> drivers/gpu/drm/v3d/v3d_sched.c:166:39: error: 'struct v3d_job' has no
>> member named 'timedout_ctra'
if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
^~
drivers/gpu/drm/v3d/v3d_sched.c:167:6: error: 'struct v3d_job' has no member
named 'timedout_ctca'
job->timedout_ctca = ctca;
^~
drivers/gpu/drm/v3d/v3d_sched.c:168:6: error: 'struct v3d_job' has no member
named 'timedout_ctra'
job->timedout_ctra = ctra;
^~
cc1: some warnings being treated as errors
vim +157 drivers/gpu/drm/v3d/v3d_sched.c
3
4 /**
5 * DOC: Broadcom V3D scheduling
6 *
7 * The shared DRM GPU scheduler is used to coordinate submitting jobs
8 * to the hardware. Each DRM fd (roughly a client process) gets its
9 * own scheduler entity, which will process jobs in order. The GPU
10 * scheduler will round-robin between clients to submit the next job.
11 *
12 * For simplicity, and in order to keep latency low for interactive
13 * jobs when bulk background jobs are queued up, we submit a new job
14 * to the HW only when it has completed the last one, instead of
15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
16 * v3d_job_dependency() to manage the dependency between bin and
17 * render, instead of having the clients submit jobs with using the
18 * HW's semaphores to interlock between them.
19 */
20
> 21 #include <linux/kthread.h>
22
23 #include "v3d_drv.h"
24 #include "v3d_regs.h"
25 #include "v3d_trace.h"
26
27 static struct v3d_job *
28 to_v3d_job(struct drm_sched_job *sched_job)
29 {
30 return container_of(sched_job, struct v3d_job, base);
31 }
32
33 static void
34 v3d_job_free(struct drm_sched_job *sched_job)
35 {
36 struct v3d_job *job = to_v3d_job(sched_job);
37
38 v3d_exec_put(job->exec);
39 }
40
41 /**
42 * Returns the fences that the bin job depends on, one by one.
43 * v3d_job_run() won't be called until all of them have been signaled.
44 */
45 static struct dma_fence *
46 v3d_job_dependency(struct drm_sched_job *sched_job,
47 struct drm_sched_entity *s_entity)
48 {
49 struct v3d_job *job = to_v3d_job(sched_job);
50 struct v3d_exec_info *exec = job->exec;
51 enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
52 struct dma_fence *fence;
53
54 fence = job->in_fence;
55 if (fence) {
56 job->in_fence = NULL;
57 return fence;
58 }
59
60 if (q == V3D_RENDER) {
61 /* If we had a bin job, the render job definitely
depends on
62 * it. We first have to wait for bin to be scheduled,
so that
63 * its done_fence is created.
64 */
65 fence = exec->bin_done_fence;
66 if (fence) {
67 exec->bin_done_fence = NULL;
68 return fence;
69 }
70 }
71
72 /* XXX: Wait on a fence for switching the GMP if necessary,
73 * and then do so.
74 */
75
76 return fence;
77 }
78
79 static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)
80 {
81 struct v3d_job *job = to_v3d_job(sched_job);
82 struct v3d_exec_info *exec = job->exec;
83 enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
84 struct v3d_dev *v3d = exec->v3d;
85 struct drm_device *dev = &v3d->drm;
86 struct dma_fence *fence;
87 unsigned long irqflags;
88
89 if (unlikely(job->base.s_fence->finished.error))
90 return NULL;
91
92 /* Lock required around bin_job update vs
93 * v3d_overflow_mem_work().
94 */
95 spin_lock_irqsave(&v3d->job_lock, irqflags);
96 if (q == V3D_BIN) {
97 v3d->bin_job = job->exec;
98
99 /* Clear out the overflow allocation, so we don't
100 * reuse the overflow attached to a previous job.
101 */
102 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
103 } else {
104 v3d->render_job = job->exec;
105 }
106 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
107
108 /* Can we avoid this flush when q==RENDER? We need to be
109 * careful of scheduling, though -- imagine job0 rendering to
110 * texture and job1 reading, and them being executed as bin0,
111 * bin1, render0, render1, so that render1's flush at bin time
112 * wasn't enough.
113 */
114 v3d_invalidate_caches(v3d);
115
116 fence = v3d_fence_create(v3d, q);
117 if (!fence)
118 return fence;
119
120 if (job->done_fence)
121 dma_fence_put(job->done_fence);
122 job->done_fence = dma_fence_get(fence);
123
124 trace_v3d_submit_cl(dev, q == V3D_RENDER,
to_v3d_fence(fence)->seqno,
125 job->start, job->end);
126
127 if (q == V3D_BIN) {
128 if (exec->qma) {
129 V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, exec->qma);
130 V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, exec->qms);
131 }
132 if (exec->qts) {
133 V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
134 V3D_CLE_CT0QTS_ENABLE |
135 exec->qts);
136 }
137 } else {
138 /* XXX: Set the QCFG */
139 }
140
141 /* Set the current and end address of the control list.
142 * Writing the end register is what starts the job.
143 */
144 V3D_CORE_WRITE(0, V3D_CLE_CTNQBA(q), job->start);
145 V3D_CORE_WRITE(0, V3D_CLE_CTNQEA(q), job->end);
146
147 return fence;
148 }
149
150 static void
151 v3d_job_timedout(struct drm_sched_job *sched_job)
152 {
153 struct v3d_job *job = to_v3d_job(sched_job);
154 struct v3d_exec_info *exec = job->exec;
155 struct v3d_dev *v3d = exec->v3d;
156 enum v3d_queue q;
> 157 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
> 158 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
159
160 /* If the current address or return address have changed, then
161 * the GPU has probably made progress and we should delay the
162 * reset. This could fail if the GPU got in an infinite loop
163 * in the CL, but that is pretty unlikely outside of an i-g-t
164 * testcase.
165 */
> 166 if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
167 job->timedout_ctca = ctca;
168 job->timedout_ctra = ctra;
169
170 schedule_delayed_work(&job->base.sched->work_tdr,
171 job->base.sched->timeout);
172 return;
173 }
174
175 mutex_lock(&v3d->reset_lock);
176
177 /* block scheduler */
178 for (q = 0; q < V3D_MAX_QUEUES; q++) {
179 struct drm_gpu_scheduler *sched = &v3d->queue[q].sched;
180
181 kthread_park(sched->thread);
182 drm_sched_hw_job_reset(sched, (sched_job->sched ==
sched ?
183 sched_job : NULL));
184 }
185
186 /* get the GPU back into the init state */
187 v3d_reset(v3d);
188
189 /* Unblock schedulers and restart their jobs. */
190 for (q = 0; q < V3D_MAX_QUEUES; q++) {
191 drm_sched_job_recovery(&v3d->queue[q].sched);
192 kthread_unpark(v3d->queue[q].sched.thread);
193 }
194
195 mutex_unlock(&v3d->reset_lock);
196 }
197
---
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