Qemu has an odd behaviour with the access to HDR (could be a qemu
bug, I'm investigating separately, but it affects current qemu's
so we should try to work around it).
Basically the internal counter that counts the reads of the 3c6
register in order to give you access to the HDR on the 5th access
is initialized in such a way that it overflows if you start doing
the 4-reads sequence right after reset, and thus fails to pickup
the subsequent write.
We work around this by doing a write before the 4 reads, which
resets the counter properly.
Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org>
---
drivers/gpu/drm/cirrus/cirrus_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.h
b/drivers/gpu/drm/cirrus/cirrus_drv.h
index 64ea597..b5685d3 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.h
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.h
@@ -74,6 +74,7 @@
#define WREG_HDR(v) \
do { \
+ WREG8(VGA_DAC_MASK, v); /* reset counter */ \
RREG8(VGA_DAC_MASK); \
RREG8(VGA_DAC_MASK); \
RREG8(VGA_DAC_MASK); \
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