On Fri, Feb 22, 2019 at 05:20:15PM +0200, Peter Ujfalusi wrote: > Hi Russell, > > On 22/02/2019 16.35, Russell King - ARM Linux admin wrote: > > On Fri, Feb 22, 2019 at 03:47:14PM +0200, Peter Ujfalusi wrote: > >> Hi, > >> > >> the original version was sent 14.04.2018: > >> https://patchwork.kernel.org/patch/10344403/ > >> > >> Changes since then: > >> - rebased on currentl drm/next > >> > >> The reset value of the register is 0, the soft reset does not reset this > >> register and if other kernel changed this the audio is going to be > >> distorted. > >> > >> It was observed when - accidentally - booted the kernel from eMMC on BBB > >> which is 3.8.13-bone79 and it sets this register to 0x0a. After reboot and > >> tda998x_reset() it remains 0x0a. > > > > Have you checked whether the input I2S stream is Philips or Left > > Justified? This is controlled by the LSB two bits. > > The am335x-boneblack-common.dtsi configures the link to i2s, which > corresponds to Philips format (the default > > > > > It appears that 3.8.13-bone79 configures the TDA998x for left- > > justified, whereas re-setting these two bits to zero will configure > > it for Philips. > > The chip reset value for the register is 0 and software reset will not > reset it if it was modified.
So I wonder why 3.8.13-bone79 configures it for left-justified. > > Bits 3:2 control the data size, but I have no information what their > > values correspond to. > > I can not find the register descriptions, can not tell what are the bits > in there. > > > Can we nail down what is required for BBB and what it doesn't care > > about. > > atm the REG_I2S_FORMAT register needs to be reset to 0. > > > and I think we should implement at least setting the I2S > > register format from the hdmi_codec_daifmt data. > > Yes, that needs to be done for sure, but without data sheet with > register descriptions I would not attempt to do that. > > > It would also be good to know what Fs value(s) BBB uses, and what > > sample sizes you have tested. > > On BBB McASP is the clock master and as I recall I have tested 44.1, 48 > KHz at least with 16 and 24 bits. Sorry, I wasn't clear enough... is the bus clocked at 32Fs for 16bit samples and 64Fs for 24bit samples, or is it 64Fs for both? > >> Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com> > >> --- > >> drivers/gpu/drm/i2c/tda998x_drv.c | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c > >> b/drivers/gpu/drm/i2c/tda998x_drv.c > >> index 7f34601bb515..72f93802d209 100644 > >> --- a/drivers/gpu/drm/i2c/tda998x_drv.c > >> +++ b/drivers/gpu/drm/i2c/tda998x_drv.c > >> @@ -722,6 +722,9 @@ tda998x_reset(struct tda998x_priv *priv) > >> > >> /* Write the default value MUX register */ > >> reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); > >> + > >> + /* Write the default to I2S_FORMAT register */ > >> + reg_write(priv, REG_I2S_FORMAT, 0x00); > >> } > >> > >> /* > >> -- > >> Peter > >> > >> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. > >> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki > >> > >> > > > > - Péter > > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki > -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel