On Wed, 27 Feb 2019, Heikki Krogerus <heikki.kroge...@linux.intel.com> wrote: > One thing that this series does not consider is the DP lane count > problem. The GPU drivers (i915 in this case) does not know is four, > two or one DP lanes in use.
Also, orientation. > I guess that is not a critical issue since there is a workaround (I > think) where the driver basically does trial and error, but ideally we > should be able to tell i915 also the pin assignment that was > negotiated with the partner device so it knows the DP lane count. Yeah, if the information is there, we'd like to know. With the orientation, there's a worst case of sixth attempt of finding out there's just one lane in a certain orientation. Couple that with link rate selection (did it not work because too high link rate or because the lanes are just not there?) we get pretty confused about what we should try. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
