Hi Andrey,
Thank you for the patch.
On Tue, Feb 26, 2019 at 11:36:08AM -0800, Andrey Smirnov wrote:
> Tc_wait_pll_lock() is always called as a follow-up for updating
s/Tc/tc/
> PLLUPDATE and PLLEN bit of a given PLL control register. To simplify
> things, merge the two operation into a single helper function
> tc_pllupdate_pllen() and convert the rest of the code to use it. No
> functional change intended.
>
> Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
> Cc: Archit Taneja <arch...@codeaurora.org>
> Cc: Andrzej Hajda <a.ha...@samsung.com>
> Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> Cc: Chris Healy <cphe...@gmail.com>
> Cc: Lucas Stach <l.st...@pengutronix.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> ---
> drivers/gpu/drm/bridge/tc358767.c | 36 +++++++++++++++++++------------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c
> b/drivers/gpu/drm/bridge/tc358767.c
> index 227f14cd2d3d..239b3aaa255d 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -390,10 +390,18 @@ static u32 tc_srcctrl(struct tc_data *tc)
> return reg;
> }
>
> -static void tc_wait_pll_lock(struct tc_data *tc)
> +static int tc_pllupdate_pllen(struct tc_data *tc, unsigned int pllctrl)
> {
> + int ret;
> +
> + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
> + if (ret)
> + return ret;
> +
> /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
> usleep_range(3000, 6000);
> +
> + return 0;
> }
>
> static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> @@ -487,11 +495,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk,
> u32 pixelclock)
> (best_mul << 0)); /* Multiplier for PLL */
>
> /* Force PLL parameter update and disable bypass */
> - tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
> -
> - tc_wait_pll_lock(tc);
> -
> - return 0;
> + return tc_pllupdate_pllen(tc, PXL_PLLCTRL);
> err:
> return ret;
> }
> @@ -568,11 +572,13 @@ static int tc_aux_link_setup(struct tc_data *tc)
> * Initially PLLs are in bypass. Force PLL parameter update,
> * disable PLL bypass, enable PLL
> */
> - tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
> - tc_wait_pll_lock(tc);
> + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL);
> + if (ret)
> + return ret;
>
> - tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
> - tc_wait_pll_lock(tc);
> + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL);
> + if (ret)
> + return ret;
>
> ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
> 1000);
> @@ -846,11 +852,13 @@ static int tc_main_link_setup(struct tc_data *tc)
> msleep(100);
>
> /* PLL setup */
> - tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
> - tc_wait_pll_lock(tc);
> + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL);
> + if (ret)
> + return ret;
>
> - tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
> - tc_wait_pll_lock(tc);
> + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL);
> + if (ret)
> + return ret;
>
> /* PXL PLL setup */
> if (tc_test_pattern) {
--
Regards,
Laurent Pinchart
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