Hi Laurent, thanks, this matches section 37.1.1 of v1.50 datasheet Reviewed-by: Jacopo Mondi <[email protected]>
Thanks j On Thu, Mar 07, 2019 at 01:23:39AM +0200, Laurent Pinchart wrote: > The D3 and E3 SoCs have different pixel clock frequency limits for the > LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode > fixup implementation accordingly. > > Signed-off-by: Laurent Pinchart <[email protected]> > --- > drivers/gpu/drm/rcar-du/rcar_lvds.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c > b/drivers/gpu/drm/rcar-du/rcar_lvds.c > index cd202157264a..b1abe737dc05 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c > +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c > @@ -515,11 +515,16 @@ static bool rcar_lvds_mode_fixup(struct drm_bridge > *bridge, > const struct drm_display_mode *mode, > struct drm_display_mode *adjusted_mode) > { > + struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); > + int min_freq; > + > /* > * The internal LVDS encoder has a restricted clock frequency operating > - * range (31MHz to 148.5MHz). Clamp the clock accordingly. > + * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to > + * 148.5MHz on all other platforms. Clamp the clock accordingly. > */ > - adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500); > + min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000; > + adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500); > > return true; > } > -- > Regards, > > Laurent Pinchart >
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