The DMFC is configured to supply a watermark signal that can be used to
temporarily increase channel priority if the FIFO runs low. Use it.
Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
---
drivers/gpu/drm/imx/ipuv3-plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3-plane.c
index d7a727a6e3d7..d81b3102b488 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -639,6 +639,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
+ ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
--
2.20.1
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