"Lespiau, Damien" <damien.lesp...@intel.com> writes: > I can't see anything in the docs about an order requirement for those.
Right, the docs don't say anything, which is a bit disconcerting. > Not sure why the other way does not make sense. Somehow disabling TX > before RX makes some sense to me (TX enabled without a ready RX looks > weird?, no data should flow as the pipe is shutdown at that point > anyway). Maybe it just does not matter? And here I figured disabling RX before TX made more sense -- otherwise the receiver wouldn't be seeing anything. In other areas of the driver, we're careful to disable receivers before senders (disable CRTC before PLL, etc). > Another detail is that disabling the PLLs seem to have an order in the > disabling sequence, TX, then RX. > > I. Disable CPU FDI Transmitter PLL > II. Disable PCH FDI Receiver PLL That ordering doesn't matter as the FDI receiver and transmitter are both disabled by that point, so they aren't talking at all. -- keith.pack...@intel.com
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