Hi, Jitao:
On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> Add dphy reset after setting lanes number to avoid dphy fifo effor.
Reviewed-by: CK Hu <ck...@mediatek.com>
>
> Signed-off-by: Jitao Shi <jitao....@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b02373b04848..8c2620ea18d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -37,6 +37,7 @@
> #define DSI_CON_CTRL 0x10
> #define DSI_RESET BIT(0)
> #define DSI_EN BIT(1)
> +#define DPHY_RESET BIT(2)
>
> #define DSI_MODE_CTRL 0x14
> #define MODE (3)
> @@ -280,6 +281,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
> mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
> }
>
> +static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
> +{
> + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
> + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
> +}
> +
> static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
> {
> mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
> @@ -650,6 +657,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> mtk_dsi_phy_timconfig(dsi);
>
> mtk_dsi_rxtx_control(dsi);
> + usleep_range(30, 100);
> + mtk_dsi_reset_dphy(dsi);
> mtk_dsi_ps_control_vact(dsi);
> mtk_dsi_set_vm_cmd(dsi);
> mtk_dsi_config_vdo_timing(dsi);
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