From: Tomi Valkeinen <tomi.valkei...@ti.com>
Reorder OMAP_BO flags and improve the comments.
Signed-off-by: Tomi Valkeinen <tomi.valkei...@ti.com>
Reviewed-by: Jean-Jacques Hiblot <jjhib...@ti.com>
---
include/uapi/drm/omap_drm.h | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/uapi/drm/omap_drm.h b/include/uapi/drm/omap_drm.h
index 1fccffef9e27..d8ee2f840697 100644
--- a/include/uapi/drm/omap_drm.h
+++ b/include/uapi/drm/omap_drm.h
@@ -38,19 +38,20 @@ struct drm_omap_param {
__u64 value; /* in (set_param), out (get_param) */
};
-#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable
(phys contiguous) */
-#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache
modes */
-#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see
tiled modes */
+/* Scanout buffer, consumable by DSS */
+#define OMAP_BO_SCANOUT 0x00000001
-/* cache modes */
-#define OMAP_BO_CACHED 0x00000000 /* default */
-#define OMAP_BO_WC 0x00000002 /* write-combine */
-#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached)
*/
+/* Buffer CPU caching mode: cached, write-combining or uncached. */
+#define OMAP_BO_CACHED 0x00000000
+#define OMAP_BO_WC 0x00000002
+#define OMAP_BO_UNCACHED 0x00000004
+#define OMAP_BO_CACHE_MASK 0x00000006
-/* tiled modes */
+/* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits.
*/
#define OMAP_BO_TILED_8 0x00000100
#define OMAP_BO_TILED_16 0x00000200
#define OMAP_BO_TILED_32 0x00000300
+#define OMAP_BO_TILED_MASK 0x00000f00
#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 |
OMAP_BO_TILED_32)
union omap_gem_size {
--
2.17.1
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