External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which designates
external memory controller as interconnect provider.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../bindings/memory-controllers/nvidia,tegra20-emc.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
index add95367640b..7566d883f921 100644
---
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -12,6 +12,9 @@ Properties:
irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
+- #interconnect-cells : Should be 1. This cell represents external memory
+ interconnect. The assignments may be found in header file
+ <dt-bindings/interconnect/tegra-icc.h>.
Child device nodes describe the memory settings for different configurations
and clock rates.
@@ -20,6 +23,7 @@ Example:
memory-controller@7000f400 {
#address-cells = < 1 >;
#size-cells = < 0 >;
+ #interconnect-cells = < 1 >;
compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>;
interrupts = <0 78 0x04>;
--
2.23.0
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