Our LVDS encoder can change the polarity of data and clock signals on
the LVDS link. Make sure we don't ignore the matching bus flags.
Signed-off-by: Maxime Ripard <max...@cerno.tech>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c81cdce6ed55..fdf143042f83 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -404,6 +404,8 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon
*tcon,
const struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
+ struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
+ const struct drm_display_info *info = &connector->display_info;
unsigned int bp;
u8 clk_delay;
u32 reg, val = 0;
@@ -449,9 +451,17 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon
*tcon,
SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
- reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
- SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
- SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
+ reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
+ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
+ reg |= SUN4I_TCON0_LVDS_IF_CLK_POL_INV;
+ else
+ reg |= SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
+
+ if (info->bus_flags & DRM_BUS_FLAG_DATA_LOW)
+ reg |= SUN4I_TCON0_LVDS_IF_DATA_POL_INV;
+ else
+ reg |= SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL;
+
if (sun4i_tcon_get_pixel_depth(encoder) == 24)
reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
else
--
git-series 0.9.1
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