The VBT fields match the DPCD data, so use the same helper.
Cc: Manasi Navare <[email protected]>
Cc: Vandita Kulkarni <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
---
drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..a4ea0e6c3286 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2494,16 +2494,11 @@ static void fill_dsc(struct intel_crtc_state
*crtc_state,
crtc_state->dsc.slice_count);
/*
- * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
- * implementation specific physical rate buffer size. Currently we use
- * the required rate buffer model size calculated in
- * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
- *
* The VBT rc_buffer_block_size and rc_buffer_size definitions
- * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
- * implementation should also use the DPCD (or perhaps VBT for eDP)
- * provided value for the buffer size.
+ * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
*/
+ vdsc_cfg->rc_model_size =
drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
+
dsc->rc_buffer_size);
/* FIXME: DSI spec says bpc + 1 for this one */
vdsc_cfg->line_buf_depth =
VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
--
2.20.1
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