Since most of the HVS channel is setup in the init function, let's move the
gamma setup there too.

Signed-off-by: Maxime Ripard <max...@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_hvs.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 2352a63fd26b..87bbd68d44db 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -201,6 +201,8 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct 
drm_crtc *crtc,
 {
        struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
        unsigned int chan = vc4_crtc_state->assigned_channel;
+       bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
+       u32 dispbkgndx;
        u32 dispctrl;
 
        /* Turn on the scaler, which will wait for vstart to start
@@ -225,6 +227,20 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, 
struct drm_crtc *crtc,
 
        HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
 
+       dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
+       dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
+       dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
+
+       HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
+                 SCALER_DISPBKGND_AUTOHS |
+                 ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
+                 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
+
+       /* Reload the LUT, since the SRAMs would have been disabled if
+        * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
+        */
+       vc4_hvs_lut_load(crtc);
+
        return 0;
 }
 
@@ -427,8 +443,6 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
        struct vc4_dev *vc4 = to_vc4_dev(dev);
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
        struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
-       struct drm_display_mode *mode = &crtc->state->adjusted_mode;
-       bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 
        if (vc4_crtc->data->hvs_output == 2) {
                u32 dispctrl;
@@ -453,16 +467,6 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
                           ~SCALER_DISPCTRL_DSP3_MUX_MASK;
                HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
        }
-
-       HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
-                 SCALER_DISPBKGND_AUTOHS |
-                 ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
-                 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
-
-       /* Reload the LUT, since the SRAMs would have been disabled if
-        * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
-        */
-       vc4_hvs_lut_load(crtc);
 }
 
 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
-- 
git-series 0.9.1
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