Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.
Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
.../memory-controllers/nvidia,tegra30-emc.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
index c243986db420..0a2e2c0d0fdd 100644
---
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
@@ -39,6 +39,15 @@ properties:
description:
Phandle of the Memory Controller node.
+ core-supply:
+ description:
+ Phandle of voltage regulator of the SoC "core" power domain.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC speedo ID mask.
+
patternProperties:
"^emc-timings-[0-9]+$":
type: object
@@ -218,6 +227,7 @@ required:
- clocks
- nvidia,memory-controller
- "#interconnect-cells"
+ - operating-points-v2
additionalProperties: false
@@ -230,6 +240,8 @@ examples:
clocks = <&tegra_car 57>;
nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ core-supply = <&vdd_core>;
#interconnect-cells = <0>;
--
2.27.0
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