Re: [PATCH v3] drm/dp: Add Additional DP2 Headers

[Tvrtko Ursulin]

Hi,

Is it my checkout only or this causes a lot of build warnings for everyone?

./include/drm/drm_dp_helper.h:1120: warning: 
"DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined
 1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0  0x2230
      |
In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35,
                 from 
./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
                 from 
./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40:
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is the 
location of the previous definition

Etc..

Regards,

Tvrtko


On 30/09/2021 22:21, Rodrigo Siqueira wrote:

Applied to drm-misc-next.

Thanks

On 09/28, Harry Wentland wrote:

On 2021-09-27 15:23, Fangzhi Zuo wrote:

Include FEC, DSC, Link Training related headers.

Change since v2
- Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT

Signed-off-by: Fangzhi Zuo <jerry....@amd.com>

Reviewed-by: Harry Wentland <harry.wentl...@amd.com>

Harry

---
This patch is based on top of the other DP2.0 work in
"drm/dp: add LTTPR DP 2.0 DPCD addresses"
---
  include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..a1df35aa6e68 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
  # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
  # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
  # define DP_FEC_BIT_ERROR_COUNT_CAP       (1 << 3)
+#define DP_FEC_CAPABILITY_1                    0x091   /* 2.0 */

/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */

  #define DP_PCON_DSC_ENCODER_CAP_SIZE        0xC       /* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
  #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2

+/* DFP Capability Extension */

+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT    0x0a3   /* 2.0 */
+
  /* Link Configuration */
  #define       DP_LINK_BW_SET                      0x100
  # define DP_LINK_RATE_TABLE               0x00    /* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;

#define DP_DSC_ENABLE 0x160 /* DP 1.4 */

  # define DP_DECOMPRESSION_EN                (1 << 0)
+#define DP_DSC_CONFIGURATION                           0x161   /* DP 2.0 */

#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */

  # define DP_PSR_ENABLE                                BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
  # define DP_RECEIVE_PORT_0_STATUS         (1 << 0)
  # define DP_RECEIVE_PORT_1_STATUS         (1 << 1)
  # define DP_STREAM_REGENERATION_STATUS      (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION     (1 << 3) /* 2.0 */

#define DP_ADJUST_REQUEST_LANE0_1 0x206

  #define DP_ADJUST_REQUEST_LANE2_3         0x207
@@ -865,6 +871,8 @@ struct drm_panel;
  # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
  # define DP_PHY_TEST_PATTERN_CP2520         0x5

+#define DP_PHY_SQUARE_PATTERN 0x249

+
  #define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
  #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
  #define       DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
  #define DP_128B132B_TRAINING_AUX_RD_INTERVAL   0x2216 /* 2.0 */
  # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f

+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230

+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256  0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT           0x2260  /* 2.0 */
+# define DP_DSC_DECODER_COUNT_MASK                     (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT                    5
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0       0x2270  /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK     (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK     (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT    1
+
  /* Protocol Converter Extension */
  /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
  #define DP_CEC_TUNNELING_CAPABILITY            0x3000